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2024-02-23phy: constify of_phandle_args in xlateKrzysztof Kozlowski1-1/+1
The xlate callbacks are supposed to translate of_phandle_args to proper provider without modifying the of_phandle_args. Make the argument pointer to const for code safety and readability. Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-by: Thierry Reding <[email protected]> Acked-by: Linus Walleij <[email protected]> Acked-by: Florian Fainelli <[email protected]> #Broadcom Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-17phy: Explicitly include correct DT includesRob Herring1-1/+1
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <[email protected]> Acked-by: Marc Kleine-Budde <[email protected]> # for drivers/phy/phy-can-transceiver.c Acked-by: Heiko Stuebner <[email protected]> Acked-by: Sergio Paracuellos <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-12-24phy: uniphier-usb3ss: fix unintended writing zeros to PHY registerRyuta NAKANISHI1-4/+6
Similar to commit 4a90bbb478db ("phy: uniphier-pcie: Fix updating phy parameters"), in function uniphier_u3ssphy_set_param(), unintentionally write zeros to other fields when writing PHY registers. Fixes: 5ab43d0f8697 ("phy: socionext: add USB3 PHY driver for UniPhier SoC") Signed-off-by: Ryuta NAKANISHI <[email protected]> Signed-off-by: Kunihiko Hayashi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-11-23phy: uniphier-ahci: Add support for Pro4 SoCKunihiko Hayashi2-5/+198
Add support for PHY interface built into ahci controller implemented in UniPhier Pro4 SoC. Pro4 SoC distinguishes it from other SoCs as "legacy" SoC, which has GIO clock line. And Pro4 AHCI-PHY needs to control additional reset lines ("pm", "tx", and "rx"). Signed-off-by: Kunihiko Hayashi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-11-23phy: uniphier-pcie: Add dual-phy support for NX1 SoCKunihiko Hayashi1-14/+34
NX1 SoC supports 2 lanes and has dual-phy. Should set appropriate configuration values to both PHY registers. Signed-off-by: Kunihiko Hayashi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-11-23phy: uniphier-pcie: Set VCOPLL clamp mode in PHY registerKunihiko Hayashi1-0/+5
Set VCOPLL clamp mode to mode 0 to avoid hardware unstable issue. Signed-off-by: Kunihiko Hayashi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-11-23phy: uniphier-pcie: Add compatible string and SoC-dependent data for NX1 SoCKunihiko Hayashi1-0/+19
Add basic support for UniPhier NX1 SoC. This includes a compatible string, SoC-dependent data, and a function that set to 2-lane mode. Signed-off-by: Kunihiko Hayashi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-11-23phy: uniphier-usb3: Add compatible string for NX1 SoCKunihiko Hayashi2-0/+8
Add basic support for UniPhier NX1 SoC. This includes a compatible string and the same SoC-dependent data as LD20/PXs3 SoCs. Signed-off-by: Kunihiko Hayashi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-06-21phy: uniphier-pcie: Fix updating phy parametersKunihiko Hayashi1-4/+7
The current driver uses a value from register TEST_O as the original value for register TEST_I, though, the value is overwritten by "param", so there is a bug that the original value isn't no longer used. The value of TEST_O[7:0] should be masked with "mask", replaced with "param", and placed in the bitfield TESTI_DAT_MASK as new TEST_I value. Fixes: c6d9b1324159 ("phy: socionext: add PCIe PHY driver support") Signed-off-by: Kunihiko Hayashi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2020-08-31phy: socionext: Add UniPhier AHCI PHY driver supportKunihiko Hayashi3-0/+332
Add a driver for PHY interface built into ahci controller implemented in UniPhier SoCs. This supports PXs2 and PXs3 SoCs. Signed-off-by: Kunihiko Hayashi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2020-03-20phy: uniphier-pcie: Add SoC-dependent phy-mode function supportKunihiko Hayashi1-7/+10
Since this phy is shared by multiple devices including USB and PCIe, it is necessary to determine which device use this phy. This patch adds SoC-dependent functions to determine a device using this phy. When there is 'socionext,syscon' property in the pcie-phy node, the driver calls SoC-dependt function instead of checking .has_syscon in SoC-dependent data. The function configures the system controller to use phy for PCIe. Signed-off-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: uniphier-pcie: Add legacy SoC support for Pro5Kunihiko Hayashi1-11/+72
Add legacy SoC support that needs to manage gio clock and reset and to skip setting unimplemented phy parameters. This supports Pro5. This specifies only 1 port use because Pro5 doesn't set it in the power-on sequence. Signed-off-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: uniphier-usb3hs: Change Rx sync mode to avoid communication failureKunihiko Hayashi1-4/+16
In case of using default parameters, communication failure might occur in rare cases. This sets Rx sync mode parameter to avoid the issue. Signed-off-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: uniphier-usb3hs: Add legacy SoC support for Pro5Kunihiko Hayashi1-15/+53
Add legacy SoC support that needs to manage gio clock and reset. This supports Pro5. Signed-off-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: uniphier-usb3ss: Add Pro5 supportKunihiko Hayashi1-0/+4
Pro5 SoC has same scheme of USB3 ss-phy as Pro4, so the data for Pro5 is equivalent to Pro4. Signed-off-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: socionext: Use devm_platform_ioremap_resource()Kunihiko Hayashi3-9/+3
Use devm_platform_ioremap_resource() to simplify the code. Signed-off-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner1-0/+1
Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-04-17phy: socionext: get optional clock by devm_clk_get_optional()Chunfeng Yun2-14/+6
Use devm_clk_get_optional() to get optional clock Cc: Kunihiko Hayashi <[email protected]> Signed-off-by: Chunfeng Yun <[email protected]> Reviewed-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2018-11-12phy: uniphier-pcie: Depend on HAS_IOMEMKunihiko Hayashi1-1/+2
The driver uses devm_ioremap_resource() which is only available when CONFIG_HAS_IOMEM is set, so the driver depends on this option. Signed-off-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2018-09-25phy: socionext: add PCIe PHY driver supportKunihiko Hayashi3-0/+250
Add a driver for PHY interface built into PCIe controller implemented in UniPhier SoCs. Signed-off-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2018-09-10phy: socionext: add USB2 PHY driver for UniPhier SoCKunihiko Hayashi3-0/+258
Add a driver for PHY interface built into USB2 controller implemented on UniPhier SoCs. This driver supports HS-PHY for Pro4 and LD11. Signed-off-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2018-09-10phy: socionext: add USB3 PHY driver for UniPhier SoCKunihiko Hayashi4-0/+789
Add a driver for PHY interface built into USB3 controller implemented in UniPhier SoCs. This driver supports High-Speed PHY and Super-Speed PHY. Signed-off-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Motoya Tanigawa <[email protected]> Signed-off-by: Masami Hiramatsu <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
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