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2023-01-17phy: qcom-qmp-ufs: Move HS Rate B register setting to tbls_hs_bManivannan Sadhasivam1-5/+32
Since now there is support for configuring the HS Rate B mode properly, let's move the register setting to tbls_hs_b struct for all SoCs. This allows the PHY to be configured in Rate A initially and then in Rate B if requested by the UFS driver. Reviewed-by: Dmitry Baryshkov <[email protected]> Tested-by: Andrew Halaney <[email protected]> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-17phy: qcom-qmp-ufs: Add support for configuring PHY in HS G4 modeManivannan Sadhasivam1-0/+9
Add separate tables_hs_g4 instance to allow the PHY driver to configure the PHY in HS G4 mode. The individual SoC configs need to supply the Rx, Tx and PCS register setting in tables_hs_g4 and the UFS driver can request the Hs G4 mode by calling phy_set_mode_ext() with submode set to UFS_HS_G4. Reviewed-by: Dmitry Baryshkov <[email protected]> Tested-by: Andrew Halaney <[email protected]> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-17phy: qcom-qmp-ufs: Add support for configuring PHY in HS Series B modeManivannan Sadhasivam1-0/+15
Add separate tables_hs_b instance to allow the PHY driver to configure the PHY in HS Series B mode. The individual SoC configs need to supply the serdes register setting in tables_hs_b and the UFS driver can request the Series B mode by calling phy_set_mode() with mode set to PHY_MODE_UFS_HS_B. Reviewed-by: Dmitry Baryshkov <[email protected]> Tested-by: Andrew Halaney <[email protected]> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-17phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tbls structManivannan Sadhasivam1-83/+113
As done for Qcom PCIe PHY driver, let's move the register settings to the common qmp_phy_cfg_tbls struct. This helps in adding any additional PHY settings needed for functionalities like HS-G4 in the future by adding one more instance of the qmp_phy_cfg_tbls. Reviewed-by: Dmitry Baryshkov <[email protected]> Tested-by: Andrew Halaney <[email protected]> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-17phy: qcom-qmp-ufs: Rename MSM8996 PHY definitionsManivannan Sadhasivam1-11/+11
Only MSM8996 is using "_ufs_" naming convention for PHY definitions instead of "_ufsphy_" as like other SoCs. So to maintain the uniformity, let's rename all of the definitions to use "_ufsphy_". Reviewed-by: Dmitry Baryshkov <[email protected]> Tested-by: Andrew Halaney <[email protected]> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-17phy: qcom-qmp-ufs: Remove _tbl suffix from qmp_phy_init_tbl definitionsManivannan Sadhasivam1-73/+73
Following the other QMP PHY drivers like PCIe, let's remove the "_tbl" suffix from the qmp_phy_init_tbl definitions. This helps in maintaining the uniformity across all of the QMP PHY drivers. Reviewed-by: Dmitry Baryshkov <[email protected]> Tested-by: Andrew Halaney <[email protected]> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-13phy: qcom-qmp: Add SM6125 UFS PHY supportLux Aliaga1-0/+5
The SM6125 UFS PHY is compatible with the one from SM6115. Add a compatible for it and modify the config from SM6115 to make them compatible with the SC8280XP binding Signed-off-by: Lux Aliaga <[email protected]> Reviewed-by: Martin Botka <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-13phy: Revert "phy: qualcomm: usb28nm: Add MDM9607 init sequence"Marijn Suijten1-13/+0
This reverts commit 557a28811c7e0286d3816842032db5eb7bb5f156. This commit introduced an init sequence from downstream DT [1] in the driver. As mentioned by the comment above the HSPHY_INIT_CFG macro for this sequence: /* * The macro is used to define an initialization sequence. Each tuple * is meant to program 'value' into phy register at 'offset' with 'delay' * in us followed. */ Instead of corresponding to offsets into the phy register, the sequence read by the downstream driver [2] is passed into ulpi_write [3] which crafts the address-value pair into a new value and writes it into the same register at USB_ULPI_VIEWPORT [4]. In other words, this init sequence is programmed into the hardware in a totally different way than downstream and is unlikely to achieve the desired result, if the hsphy is working at all. An alternative method needs to be found to write these init values at the desired location. Fortunately mdm9607 did not land upstream yet [5] and should have its compatible revised to use the generic one, instead of a compatible that writes wrong data to the wrong registers. [1]: https://android.googlesource.com/kernel/msm/+/android-7.1.0_r0.2/arch/arm/boot/dts/qcom/mdm9607.dtsi#585 [2]: https://android.googlesource.com/kernel/msm/+/android-7.1.0_r0.2/drivers/usb/phy/phy-msm-usb.c#4183 [3]: https://android.googlesource.com/kernel/msm/+/android-7.1.0_r0.2/drivers/usb/phy/phy-msm-usb.c#468 [4]: https://android.googlesource.com/kernel/msm/+/android-7.1.0_r0.2/drivers/usb/phy/phy-msm-usb.c#418 [5]: https://lore.kernel.org/linux-arm-msm/[email protected]/ Reported-by: Michael Srba <[email protected]> Signed-off-by: Marijn Suijten <[email protected]> Reviewed-by: Stephan Gerhold <[email protected]> Reviewed-by: Bryan O'Donoghue <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-13phy: qcom-qmp-usb: Add Qualcomm SM6115 / SM4250 USB3 PHY supportBhupesh Sharma1-0/+3
Enable SM6115 / SM4250 USB3 PHY support by adding the qmp_phy_cfg data. Since this PHY is the same as the one used on QCM2290, reuse the QCM2290 qmp_phy_cfg data already available. Signed-off-by: Bhupesh Sharma <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-13phy: qcom-qmp-usb: Fix QSERDES_V3_RX_UCDR_PI_CONTROLS init valBhupesh Sharma1-1/+1
As per the Qualcomm QMP v3 PHY programming guide document, QSERDES_V3_RX_UCDR_PI_CONTROLS configuration should be set to an initial configuration value of 0x80. Fix the same. Signed-off-by: Bhupesh Sharma <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-12phy: qcom-qmp: move type-specific headers to particular driverDmitry Baryshkov5-14/+17
Remove QMP PHY type-specific headers inclusion from the common header and move them to the specific PHY drivers to cleanup the namespaces used by different drivers. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-12phy: qcom-qmp-usb: fix regs layout arraysDmitry Baryshkov1-11/+13
Drop qcm2290_usb3phy_regs_layout, it is a duplicate of qmp_v3_usb3phy_regs_layout. Introduce qmp_v5_usb3phy_regs_layout to be used for sm8350 and sc8280xp. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-12phy: qcom-qmp-usb: rework regs layout arraysDmitry Baryshkov2-26/+29
Use symbolic names for the values inside reg layout arrays. New register names are added following the PCS register layout that is used by the particular PHY. Note: ipq8074 tables appear to use a mixture of v2 and v3 registers. This might need additional fixes. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-12phy: qcom-qmp-usb: remove QPHY_PCS_MISC_TYPEC_CTRL regDmitry Baryshkov1-3/+0
The QPHY_PCS_MISC_TYPEC_CTRL register is not used, remove it from register layout. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-12phy: qcom-qmp-usb: remove QPHY_PCS_LFPS_RXTERM_IRQ_STATUS regDmitry Baryshkov2-6/+1
The QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register is not used, remove it from register layout. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-12phy: qcom-qmp-ufs: rename regs layout arraysDmitry Baryshkov2-16/+21
Rename regs layouts to follow the QMP PHY version. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-12phy: qcom-qmp-ufs: rework regs layout arraysDmitry Baryshkov3-9/+17
Use symbolic names for the values inside reg layout arrays. New register names are added following the PCS register layout that is used by the particular PHY. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-12phy: qcom-qmp-ufs: split UFS-specific v2 PCS registers to a separate headerDmitry Baryshkov4-20/+30
Follow other QMP headers, split and rename UFS-specific PCS registers to ease comparing regs differences. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-12phy: qcom-qmp-pcie-msm8996: rework regs layout arraysDmitry Baryshkov1-3/+3
Use symbolic names for the values inside reg layout arrays. New register names are added following the PCS register layout that is used by the particular PHY. Note: ipq8074 tables appear to use a mixture of v2 and v3 registers. This might need additional fixes. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-12phy: qcom-qmp-pcie: rename regs layout arraysDmitry Baryshkov2-26/+30
Rename regs layouts to follow the QMP PHY version. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-12phy: qcom-qmp-pcie: rework regs layout arraysDmitry Baryshkov2-16/+20
Use symbolic names for the values inside reg layout arrays. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-12phy: qcom-qmp: remove duplicate v5_5nm register definitionsDmitry Baryshkov1-5/+0
Remove duplicate defines from phy-qcom-qmp-qserdes-txrx-v5_5nm.h Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-12phy: qcom-qmp: fix typo in QSERDES_COM_CMN_RSVD5 valueDmitry Baryshkov1-1/+1
Fix typo in QSERDES_COM_CMN_RSVD5 register definition. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-12phy: qcom-qmp-ufs: provide symbol clocksDmitry Baryshkov1-0/+57
Register three UFS symbol clocks (ufs_rx_symbol_0_clk_src, ufs_rx_symbol_1_clk_src ufs_tx_symbol_0_clk_src). Register OF clock provider to let other devices link these clocks through the DT. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-12phy: qualcomm: pcie2: register as clock providerDmitry Baryshkov1-1/+5
Register pcie2 PHY as a clock provider to enable using it in the DT-based clock lookup. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-12phy: qcom-qmp-pcie: add support for sm8350 platformDmitry Baryshkov1-1/+119
Add support for a single-lane and two-lane PCIe PHYs found on Qualcomm SM8350 platform. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-12phy: qcom-qmp-pcie: rename the sm8450 gen3 PHY config tablesDmitry Baryshkov1-9/+9
SM8350 PHY config tables are mostly the same as SM8450 gen3 PHY config tables. Rename generic tables to remove x1 suffix. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-12phy: qcom-qmp-pcie: split sm8450 gen3 PHY config tablesDmitry Baryshkov1-6/+20
SM8350 PHY config tables are mostly the same as SM8450 gen3 PHY config tables. Split these tables to be used by SM8350 config. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-11-24phy: qcom-qmp-pcie: drop redundant clock allocationJohan Hovold1-5/+3
Since the QMP driver split, there is no reason to allocate the fixed-rate pipe clock structure separately from the driver data. Signed-off-by: Johan Hovold <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-11-24phy: qcom-qmp-usb: drop redundant clock allocationJohan Hovold1-5/+3
Since the QMP driver split, there is no reason to allocate the fixed-rate pipe clock structure separately from the driver data. Signed-off-by: Johan Hovold <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-11-24phy: qcom-qmp: drop unused type headerJohan Hovold4-8/+0
The PHY type defines are no longer used in the PCIe, UFS and USB QMP drivers so drop the corresponding include. Signed-off-by: Johan Hovold <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-11-24phy: qcom-qmp-usb: drop sc8280xp reference-clock sourceJohan Hovold1-8/+12
The source clock for the reference clock is not used by the PHY directly and should not be described by the devicetree (instead this relationship should be modelled in the clock driver). Drop the driver management of the reference-clock source for SC8280XP. Once the other clock drivers have been updated, the corresponding change can be done also for the other QMP v4 platforms. Signed-off-by: Johan Hovold <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-11-24phy: qcom-qmp-combo: add support for updated sc8280xp bindingJohan Hovold1-11/+134
Add support for the new SC8280XP binding. Note that the binding does not try to describe every register subregion and instead the driver holds the corresponding offsets. Also note that (possibly) unlike on earlier platforms, the TX registers are used by both the USB and DP implementation. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-11-24phy: qcom-qmp-combo: rename DP_PHY register pointerJohan Hovold1-69/+70
The DP_PHY registers have erroneously been referred to as "PCS" registers since DisplayPort support was added to the QMP drivers (including in the devicetree binding). Rename the corresponding pointer to match the register names. Note that the repeated "dp" in the field name is intentional and this DP register block is called "DP_PHY" (not just "PHY"). Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-11-24phy: qcom-qmp-combo: rename common-register pointersJohan Hovold1-12/+12
The common registers are shared by the USB and DP parts of the PHY so drop the misleading "dp" prefix from the corresponding pointers. Note that the "DP" prefix could also be dropped from the corresponding defines, but leave that in place for now. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-11-24phy: qcom-qmp-combo: clean up DP clock callbacksJohan Hovold1-19/+14
Clean up the DP clock callbacks somewhat by dropping the redundant "qcom" prefix and removing line breaks after type specifiers. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-11-24phy: qcom-qmp-combo: separate clock and provider registrationJohan Hovold1-24/+20
In preparation for supporting devicetree bindings which do not use child nodes, separate clock registration from clock-provider registration. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-11-24phy: qcom-qmp-combo: add clock registration helperJohan Hovold1-5/+17
In preparation for supporting devicetree bindings which do not use child nodes, add a clock registration helper to handle the registration of both the USB and DP clocks. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-11-24phy: qcom-qmp-combo: drop redundant clock allocationJohan Hovold1-5/+2
Since the QMP driver split, there is no reason to allocate the fixed-rate pipe clock structure separately from the driver data. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-11-24phy: qcom-qmp-combo: drop redundant clock structureJohan Hovold1-35/+17
Drop the unnecessary DP clock structure and instead store the clocks directly in the driver data. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-11-24phy: qcom-qmp-combo: generate pipe clock nameJohan Hovold1-6/+3
In preparation for supporting devicetree bindings which do not use child nodes, generate also the USB3 pipe clock name based on the platform device name as is done for the DP clocks. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-11-24phy: qcom-qmp-combo: restructure PHY creationJohan Hovold1-41/+48
In preparation for supporting devicetree bindings which do not use child nodes, move the PHY creation to probe() proper and parse the serdes, dp_com and dp_serdes resources in a dedicated legacy devicetree helper. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-11-24phy: qcom-qmp-combo: drop v4 reference-clock sourceJohan Hovold1-1/+1
The source clock for the reference clock should not be described by the devicetree and instead this relationship should be modelled in the clock driver. Drop the management of the source clock from the driver for SC8180X and SC8280XP. Note that support for the former is not yet in mainline. Also note that the binding has never been updated to describe the v4 clocks for SC8180X. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-11-24phy: qcom-qmp-combo: clean up DP callback namesJohan Hovold1-41/+41
Clean up and unify the DP callbacks by dropping the redundant "qcom" and "phy" prefix and infix and by using a common naming scheme ("qmp" + version + callback name). Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-11-24phy: qcom-qmp-combo: clean up probe initialisationJohan Hovold1-34/+27
Stop abusing the driver data pointer and instead pass the driver state structure directly to the initialisation helpers during probe. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-11-24phy: qcom-qmp-combo: clean up device-tree parsingJohan Hovold1-54/+28
Since the QMP driver split there will be precisely two child nodes so drop the obsolete iteration construct. While at it, drop the verbose error logging that would have been printed also on probe deferrals. Note that there is no need to check if there are additional child nodes (the kernel is not a devicetree validator), but let's return an error if either child node is missing. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-11-24phy: qcom-qmp-combo: merge driver dataJohan Hovold1-376/+312
The QMP combo driver manages a single PHY (even if it provides two interfaces for USB and DP, respectively) so merge the old qcom_qmp and qmp_phy structures and drop the PHY array. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-11-24phy: qcom-qmp-combo: merge USB and DP configurationsJohan Hovold1-125/+57
It does not really make any sense to keep separate configuration structures for the USB and DP parts of the same PHY so merge them. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-11-24phy: qcom-qmp-combo: drop lanes config parameterJohan Hovold1-42/+20
Since the QMP driver split there is really no need for the 'lanes' configuration parameter as all of these USB-C PHYs support dual-lane SuperSpeed USB and quad-lane (uni-directional) DP (even if the driver still only supports CC1 orientation using lanes 2 and 3). Signed-off-by: Johan Hovold <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-11-24phy: qcom-qmp-combo: add DP configuration tablesJohan Hovold1-21/+24
In preparation for merging the USB and DP configurations, add dedicated pointers for the DP serdes and tx tables to the configurations. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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