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2023-05-16phy: qcom-qusb2: add QUSB2 support for IPQ9574Varadarajan Narayanan1-0/+3
Add the phy init sequence for the Super Speed ports found on IPQ9574. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Varadarajan Narayanan <[email protected]> Link: https://lore.kernel.org/r/7c67e9e92227add6544009092adbd400c3cb47db.1683630932.git.quic_varada@quicinc.com Signed-off-by: Vinod Koul <[email protected]>
2023-05-08phy: qcom-qmp: Add SA8775P USB3 UNI phyShazad Hussain1-0/+45
The SA8775P platform has 5nm USB3 UNI phy attached to the USB0 and USB1 controllers. Add QMP PHY config, pcs entries and support for the new compatible for SA8775P platform. Signed-off-by: Shazad Hussain <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-05-08phy: qcom-qmp-pcie-msm8996: fix init-count imbalanceJohan Hovold1-2/+3
The init counter is not decremented on initialisation errors, which prevents retrying initialisation. Add the missing decrement on initialisation errors so that the counter reflects the state of the device. Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") Cc: [email protected] # 4.12 Signed-off-by: Johan Hovold <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-05-08phy: qcom-qmp-combo: fix init-count imbalanceJohan Hovold1-2/+3
The init counter is not decremented on initialisation errors, which prevents retrying initialisation and can lead to the runtime suspend callback attempting to disable resources that have never been enabled. Add the missing decrement on initialisation errors so that the counter reflects the state of the device. Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") Cc: [email protected] # 4.12 Signed-off-by: Johan Hovold <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-04-12phy: qualcomm: phy-qcom-qmp-ufs: add definitions for sa8775pBartosz Golaszewski1-0/+37
Add QMP PHY config for sa8775p and add support for the new compatible. Signed-off-by: Bartosz Golaszewski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-04-10phy: qcom-qmp-pcie: drop sdm845_qhp_pcie_rx_tblDmitry Baryshkov1-5/+0
The SDM845 QHP PHY doesn't have designated RX region. Corresponding RX table is empty, so we can drop it completely. Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-04-10phy: qcom-qmp-pcie: sc8180x PCIe PHY has 2 lanesDmitry Baryshkov1-1/+1
All PCIe PHYs on sc8180x platform have 2 lanes, so change the number of lanes to 2. Fixes: f839f14e24f2 ("phy: qcom-qmp: Add sc8180x PCIe support") Cc: [email protected] # 5.15 Sgned-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-03-31phy: qcom-qmp-ufs: Add SM7150 supportDavid Wronek1-0/+61
Add the tables and constants for init sequences for UFS QMP phy found in SM7150 SoC. Signed-off-by: David Wronek <[email protected]> Signed-off-by: Danila Tikhonov <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-03-31phy: qcom-qmp: Add support for SDX65 QMP PCIe PHYRohit Agarwal4-0/+193
The PCIe PHY version used in SDX65 is v5.20 which has different register offsets compared to the v5.0x and v4.0x PHYs. So separate register defines are used for init sequence and PHY status. Signed-off-by: Rohit Agarwal <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-03-31phy: qcom-qmp-combo: use qmp_combo_offsets_v3 instead of _v6Dmitry Baryshkov1-17/+1
The qmp_combo_offsets_v3 table is already used for v3 and v4 PHYs. Reuse it for v6 too, dropping the separate qmp_combo_offsets_v6. Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-03-31phy: qcom-qmp-combo: fix v3 offsets tableDmitry Baryshkov1-0/+1
SM8350 and SM8450 use qmp_combo_offsets_v3 table, which doesn't have PCS_USB offset. Add the usb3_pcs_usb entry to program correct registers while setting up sm8350 and sm8450 USB+DP combo PHYs. Fixes: 05bd18348b88 ("phy: qcom-qmp-combo: Add config for SM6350") Cc: Neil Armstrong <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-03-20phy: qualcomm: phy-qcom-ipq806x-sata: Convert to platform remove callback ↵Uwe Kleine-König1-4/+2
returning void The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-03-20phy: qualcomm: phy-qcom-eusb2-repeater: Convert to platform remove callback ↵Uwe Kleine-König1-5/+3
returning void The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-03-20phy: qualcomm: phy-qcom-apq8064-sata: Convert to platform remove callback ↵Uwe Kleine-König1-4/+2
returning void The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-03-20phy: qcom-qmp-pcie: Add RC init sequence for SDX55Manivannan Sadhasivam2-1/+50
Add PCIe RC init sequence making use of the common init sequence. The RC mode additionally requires REFCLK_DRV_DSBL bit to set during powerup and powerdown. Signed-off-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-03-20phy: qcom-qmp-pcie: Split out EP related init sequence for SDX55Manivannan Sadhasivam1-14/+28
In preparation for adding RC support, let's split out the EP related init sequence so that the common sequence could be reused by RC as well. Signed-off-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-02-16phy: qcom: phy-qcom-snps-eusb2: Add support for eUSB2 repeaterNeil Armstrong1-1/+18
For USB 2.0 compliance, eUSB2 needs a repeater. The PHY needs to initialize and reset it. So add repeater support Co-developed-by: Abel Vesa <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-02-16phy: qcom: Add QCOM SNPS eUSB2 repeater driverAbel Vesa3-0/+269
PM8550B contains a eUSB2 repeater used for making the eUSB2 from SM8550 USB 2.0 compliant. This can be modelled SW-wise as a Phy. So add a new phy driver for it. Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-02-14Merge tag 'phy-fixes-6.2' into nextVinod Koul1-13/+0
Merge fixes tag pulled into mainline by Linus into phy/next due to dependency on amlogic patches
2023-02-13phy: qcom: snps-eusb2: Add missing headersVinod Koul1-0/+2
The driver was missing to include couple of headers explictly which causes build to fail on other archs drivers/phy/qualcomm/phy-qcom-snps-eusb2.c: In function 'qcom_snps_eusb2_hsphy_write_mask': drivers/phy/qualcomm/phy-qcom-snps-eusb2.c:147:15: error: implicit declaration of function 'readl_relaxed' [-Werror=implicit-function-declaration] 147 | reg = readl_relaxed(base + offset); | ^~~~~~~~~~~~~ drivers/phy/qualcomm/phy-qcom-snps-eusb2.c:150:9: error: implicit declaration of function 'writel_relaxed' [-Werror=implicit-function-declaration] 150 | writel_relaxed(reg, base + offset); | ^~~~~~~~~~~~~~ drivers/phy/qualcomm/phy-qcom-snps-eusb2.c: In function 'qcom_eusb2_default_parameters': drivers/phy/qualcomm/phy-qcom-snps-eusb2.c:161:42: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration] 161 | FIELD_PREP(PHY_CFG_TX_PREEMP_TUNE_MASK, 0)); | ^~~~~~~~~~ Fix this by adding bitfield.h and iopoll.h explictly Fixes: 80090810f5d3 ("phy: qcom: Add QCOM SNPS eUSB2 driver") Reported-by: Stephen Rothwell <[email protected]> Reported-by: kernel test robot <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2023-02-10phy: qcom-qmp-combo: Add support for SM8550Abel Vesa1-7/+401
Add SM8550 specific register layout and table configs. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-02-10phy: qcom-qmp: Add v6 DP register offsetsAbel Vesa1-0/+4
The new SM8550 SoC bumps up the HW version of QMP phy to v6. Add the new DP specific offsets in the generic qmp header file. Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-02-10phy: qcom-qmp: pcs-usb: Add v6 register offsetsAbel Vesa2-0/+32
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB. Add the new PCS USB specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-02-10phy: qcom: Add QCOM SNPS eUSB2 driverAbel Vesa3-0/+432
The SM8550 SoC uses Synopsis eUSB2 PHY for USB 2.0. Add a new driver for it. The driver is based on a downstream implementation. Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-02-10phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEsAbel Vesa1-1/+343
Add the SM8550 both g4 and g3 configurations. In addition, there is a new "lane shared" table that needs to be configured for g4, along with the No-CSR list of resets. The no-CSR allows resetting the PHY without actually dropping the PHY configuration. The no-CSR needs to be deasserted only after the PHY has been configured and the PLL has stabilized. Co-developed-by: Neil Armstrong <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-02-10phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsetsAbel Vesa2-0/+33
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new lane shared PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-02-10phy: qcom-qmp: qserdes-txrx: Add v6.20 register offsetsAbel Vesa2-0/+46
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new qserdes TX RX PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-02-10phy: qcom-qmp: pcs-pcie: Add v6.20 register offsetsAbel Vesa2-0/+24
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new PCS PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-02-10phy: qcom-qmp: pcs-pcie: Add v6 register offsetsAbel Vesa2-0/+16
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new PCS PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-02-10phy: qcom-qmp: pcs: Add v6.20 register offsetsAbel Vesa2-0/+20
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new PCS offsets in a dedicated header file. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-02-10phy: qcom-qmp: pcs: Add v6 register offsetsAbel Vesa2-0/+18
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new PCS offsets in a dedicated header file. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-02-10phy: qcom: com-qmp-combo: add SM8350 & SM8450 supportNeil Armstrong1-0/+170
Copy the USB tables from the QMP USB3 PHY driver and add the missing DP tables from downstream to enable USB3/DP on the SM8350 and SM8450 platforms. Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230206-topic-sm8350-upstream-usb-dp-combo-phy-v1-2-ed849ae6b849@linaro.org Signed-off-by: Vinod Koul <[email protected]>
2023-02-03phy: qcom-qmp: Introduce Kconfig symbols for discrete driversStephen Boyd2-10/+52
Introduce a config option for each QMP PHY driver now that the QMP PHY mega-driver has been split up into different modules. This allows kernel configurators to limit the binary size of the kernel by only compiling in the QMP PHY driver that they need. Leave the old config QCOM_QMP in place and make it into a menuconfig so that 'make olddefconfig' continues to work. Furthermore, set the default of the new Kconfig symbols to be QCOM_QMP so that the transition is smooth. Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Signed-off-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-02-02phy: qcom-qmp-combo: Add config for SM6350Luca Weiss1-2/+137
Add the tables and config for the combo phy found on SM6350. Signed-off-by: Luca Weiss <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-02-02phy: qcom-qmp-ufs: Add SM8550 supportAbel Vesa1-0/+96
Add SM8550 specific register layout and table configs. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-02-02phy: qcom-qmp: pcs-ufs: Add v6 register offsetsAbel Vesa2-0/+32
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new PCS UFS specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-02-02phy: qcom-qmp: qserdes-txrx-ufs: Add v6 register offsetsAbel Vesa2-0/+32
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new qserdes TX RX but UFS specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-02-02phy: qcom-qmp: qserdes-txrx: Add v6 register offsetsAbel Vesa2-0/+78
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new qserdes TX RX offsets in a dedicated header file. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-02-02phy: qcom-qmp: qserdes-com: Add v6 register offsetsAbel Vesa2-0/+84
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new qserdes com offsets in a dedicated header file. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-18phy: qcom-qmp-usb: fix the regs layout table for sdx65 uniphy PHYDmitry Baryshkov1-1/+1
The sdx64 uniphy gen3x1 PHY references the qmp_v4_usb3phy_regs_layout while the PHY itself uses v5 regs. While there are only minor differences between v4 and v5 regs and none of them concerns registers mentions in regs_layout, switch the PHY to use qmp_v5_usb3phy_regs_layout, to remove possible confusion. Fixes: 14d98d3bf70e ("phy: qcom-qmp-usb: fix regs layout arrays") Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-18phy: qcom-qmp-pcie: fix the regs layout table for sm8450 gen3x1 PHYDmitry Baryshkov1-1/+1
The sm8450 gen3x1 PHY references the pciephy_v4_regs_layout while the PHY itself uses v5 regs. While there are only minor differences between v4 and v5 regs and none of them concerns registers mentions in regs_layout, switch the PHY to use pciephy_v5_regs_layout to remove possible confusion. Fixes: bbe207a1aba1 ("phy: qcom-qmp-pcie: rename regs layout arrays") Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-18phy: qcom-qmp-combo: rework regs layout arraysDmitry Baryshkov1-12/+12
Use symbolic names for the values inside reg layout arrays. New register names are added following the PCS register layout that is used by the particular PHY. Note: ipq8074 tables appear to use a mixture of v2 and v3 registers. This might need additional fixes. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-18phy: qcom-qmp-combo: remove QPHY_PCS_LFPS_RXTERM_IRQ_STATUS regDmitry Baryshkov1-5/+0
The QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register is not used, remove it from register layout. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-18phy: qualcomm: qmp-ufs: rename qmp_ufs_offsets_v5 to qmp_ufs_offsetsDmitry Baryshkov1-3/+3
All currently known QMP UFS PHYs have the same offsets for register sub-regions. Instead of using qmp_ufs_offsets_v5 for older generations of PHYs, rename the offsets struct instance to remove _v5 suffix. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-17phy: qcom-qmp-ufs: Add HS G4 mode support to SC8280XP SoCManivannan Sadhasivam1-0/+8
UFS PHY in SC8280XP SoC is capable of operating at HS G4 mode and the init sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance reusing the G4 init sequence of SM8350. Reviewed-by: Dmitry Baryshkov <[email protected]> Tested-by: Andrew Halaney <[email protected]> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-17phy: qcom-qmp-ufs: Add HS G4 mode support to SM8450 SoCManivannan Sadhasivam1-0/+8
UFS PHY in SM8450 SoC is capable of operating at HS G4 mode and the init sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance reusing the G4 init sequence of SM8350. Reviewed-by: Dmitry Baryshkov <[email protected]> Tested-by: Andrew Halaney <[email protected]> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-17phy: qcom-qmp-ufs: Add HS G4 mode support to SM8350 SoCManivannan Sadhasivam1-0/+36
UFS PHY in SM8350 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. Reviewed-by: Dmitry Baryshkov <[email protected]> Tested-by: Andrew Halaney <[email protected]> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-17phy: qcom-qmp-ufs: Avoid setting HS G3 specific registersManivannan Sadhasivam1-7/+0
SM8350 default init sequence sets some PCS registers to HS G3, thereby disabling HS G4 mode. This has the effect on MPHY capability negotiation between the host and the device during link startup and causes the PA_MAXHSGEAR to G3 irrespective of device max gear. Due to that, the agreed gear speed determined by the UFS core will become G3 only and the platform won't run at G4. So, let's remove setting these registers for SM8350 as like other G4 compatible platforms. One downside of this is that, when the board design uses non-G4 compatible device, then MPHY will continue to run in the default mode (G4) even if UFSHCD runs in G3. But this is the case for other platforms as well. Tested-by: Andrew Halaney <[email protected]> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-17phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoCManivannan Sadhasivam2-1/+62
UFS PHY in SM8250 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. This also requires a separate qmp_phy_cfg for SM8250 instead of reusing SM8150. Reviewed-by: Dmitry Baryshkov <[email protected]> Tested-by: Andrew Halaney <[email protected]> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-01-17phy: qcom-qmp-ufs: Add HS G4 mode support to SM8150 SoCManivannan Sadhasivam1-0/+36
UFS PHY in SM8150 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. Reviewed-by: Dmitry Baryshkov <[email protected]> Tested-by: Andrew Halaney <[email protected]> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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