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2024-01-23phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550Can Guo4-22/+159
On SM8550, two sets of UFS PHY settings are provided, one set is to support HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY settings are programming different values to different registers, mixing the two sets and/or overwriting one set with another set is definitely not blessed by UFS PHY designers. To add HS-G5 support for SM8550, split the two sets of PHY settings into their dedicated overlay tables, only the common parts of the two sets of PHY settings are left in the .tbls. Consider we are going to add even higher gear support in future, to avoid adding more tables with different names, rename the .tbls_hs_g4 and make it an array, a size of 2 is enough as of now. In this case, .tbls alone is not a complete set of PHY settings, so either tbls_hs_overlay[0] or tbls_hs_overlay[1] must be applied on top of the .tbls to become a complete set of PHY settings. Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Can Guo <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2024-01-23phy: qcom: qmp-ufs: Add SC7180 supportDavid Wronek1-0/+3
The SC7180 UFS PHY is identical to the one found on SM7150. Add a compatible for it. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: David Wronek <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2024-01-18Merge tag 'phy-for-6.8' of ↵Linus Torvalds15-9/+978
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "New Support: - Qualcomm SM8650 UFS, PCIe and USB/DP Combo PHY, eUSB2 PHY, SDX75 USB3, X1E80100 USB3 support - Mediatek MT8195 support - Rockchip RK3128 usb2 support - TI SGMII mode for J784S4 Updates: - Qualcomm v7 register offsets updates - Mediatek tphy support for force phy mode switch" * tag 'phy-for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (34 commits) phy: ti: j721e-wiz: Add SGMII support in WIZ driver for J784S4 phy: ti: gmii-sel: Enable SGMII mode for J784S4 phy: qcom-qmp-usb: Add Qualcomm X1E80100 USB3 PHY support dt-bindings: phy: qcom,sc8280xp-qmp-usb3-uni: Add X1E80100 USB PHY binding phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Document X1E80100 compatible dt-bindings: phy: qcom: snps-eusb2: Document the X1E80100 compatible phy: mediatek: tphy: add support force phy mode switch dt-bindings: phy: mediatek: tphy: add a property for force-mode switch phy: phy-can-transceiver: insert space after include phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY Settings dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: fix path to header phy: renesas: phy-rcar-gen2: use select for GENERIC_PHY phy: qcom-qmp: qserdes-txrx: Add v7 register offsets phy: qcom-qmp: qserdes-txrx: Add V6 N4 register offsets phy: qcom-qmp: qserdes-com: Add v7 register offsets phy: qcom-qmp: pcs-usb: Add v7 register offsets phy: qcom-qmp: pcs: Add v7 register offsets phy: qcom-qmp: qserdes-txrx: Add some more v6.20 register offsets phy: qcom-qmp: qserdes-com: Add some more v6 register offsets ...
2023-12-21phy: qcom-qmp-usb: Add Qualcomm X1E80100 USB3 PHY supportAbel Vesa1-0/+171
The X1E80100 platform has two instances of the USB3 UNI phy attached to the multi-port USB controller, add definition for these. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/20231122-phy-qualcomm-usb3-uniphy-x1e80100-v3-2-273814c300f8@linaro.org Signed-off-by: Vinod Koul <[email protected]>
2023-12-21phy: qcom-qmp-combo: Add x1e80100 USB/DP combo physAbel Vesa1-0/+170
The X1E80100 has three copies of an USB/DP compbo PHY, add support for this to the Qualcomm QMP PHY driver. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-12-21phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY SettingsCan Guo2-9/+20
The registers, which are being touched in current SM8550 UFS PHY settings, and the values being programmed are mainly the ones working for HS-G4 mode, meanwhile, there are also a few ones somehow taken from HS-G5 PHY settings. However, even consider HS-G4 mode only, some of them are incorrect and some are missing. Rectify the HS-G4 PHY settings by strictly aligning with the SM8550 UFS PHY Hardware Programming Guide suggested HS-G4 PHY settings. Fixes: 1679bfef906f ("phy: qcom-qmp-ufs: Add SM8550 support") Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Can Guo <[email protected]> Tested-by: Neil Armstrong <[email protected]> # on SM8550-QRD Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-12-21phy: qcom-qmp: qserdes-txrx: Add v7 register offsetsAbel Vesa2-0/+79
The X1E80100 platform bumps the HW version of QMP phy to v7 for USB and PCIE. Add the new qserdes TX RX offsets in a dedicated header file. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-7-dfd1c375ef61@linaro.org Signed-off-by: Vinod Koul <[email protected]>
2023-12-21phy: qcom-qmp: qserdes-txrx: Add V6 N4 register offsetsAbel Vesa2-0/+52
There is a variant of V6 offsets that are different, the QMP PHY N4, and it is found on the X1E80100 platform. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-6-dfd1c375ef61@linaro.org Signed-off-by: Vinod Koul <[email protected]>
2023-12-21phy: qcom-qmp: qserdes-com: Add v7 register offsetsAbel Vesa2-0/+89
The X1E80100 platform bumps the HW version of QMP phy to v7 for USB and PCIE g3x2. Add the new qserdes com offsets in a dedicated header file. Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-5-dfd1c375ef61@linaro.org Signed-off-by: Vinod Koul <[email protected]>
2023-12-21phy: qcom-qmp: pcs-usb: Add v7 register offsetsAbel Vesa1-0/+17
The X1E80100 platform bumps the HW version of QMP phy to v7 for USB. Add the new PCS USB specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-4-dfd1c375ef61@linaro.org Signed-off-by: Vinod Koul <[email protected]>
2023-12-21phy: qcom-qmp: pcs: Add v7 register offsetsAbel Vesa2-0/+34
The X1E80100 platform bumps the HW version of QMP phy to v7 for USB, and PCIe. Add the new PCS offsets in a dedicated header file. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-3-dfd1c375ef61@linaro.org Signed-off-by: Vinod Koul <[email protected]>
2023-12-21phy: qcom-qmp: qserdes-txrx: Add some more v6.20 register offsetsAbel Vesa1-0/+4
Add some missing v6.20 registers offsets that are needed by the new Snapdragon X Elite (X1E80100) platform. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-2-dfd1c375ef61@linaro.org Signed-off-by: Vinod Koul <[email protected]>
2023-12-21phy: qcom-qmp: qserdes-com: Add some more v6 register offsetsAbel Vesa2-0/+6
Add some missing V6 registers offsets that are needed by the new Snapdragon X Elite (X1E80100) platform. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-1-dfd1c375ef61@linaro.org Signed-off-by: Vinod Koul <[email protected]>
2023-12-04phy: qcom: qmp-combo: switch to DRM_AUX_BRIDGEDmitry Baryshkov2-43/+3
Switch to using the new DRM_AUX_BRIDGE helper to create the transparent DRM bridge device instead of handcoding corresponding functionality. Acked-by: Vinod Koul <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-11-27phy: qcom-qmp-usb: Add Qualcomm SDX75 USB3 PHY supportRohit Agarwal1-0/+173
Add support for USB3 QMP PHY found in SDX75 platform. Signed-off-by: Rohit Agarwal <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-11-16phy: qcom: qmp-combo: add QMP USB3/DP PHY tables for SM8650Neil Armstrong1-0/+4
Add QMP USB3/DP Combo PHY support for the SM8650 platform. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-11-16phy: qcom: qmp-pcie: add QMP PCIe PHY tables for SM8650Neil Armstrong1-0/+65
Add QMP PCIe PHY support for the SM8650 platform. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-11-16phy: qcom: qmp-ufs: add QMP UFS PHY tables for SM8650Neil Armstrong3-0/+94
Add QMP UFS PHY support for the SM8650 platform. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-10-23phy: qcom-qmp-pcie: add endpoint support for sa8775pMrinmay Sarkar2-0/+39
Add support for dual lane end point mode PHY found on sa8755p platform. Signed-off-by: Mrinmay Sarkar <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-10-13phy: qcom-qmp-combo: use v6 registers in v6 regs layoutDmitry Baryshkov3-7/+12
Make sure that we use only v6 registers in qmp_v6_usb3phy_regs_layout. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-10-13phy: qcom-qmp-usb: move PCS v6 register to the proper headerDmitry Baryshkov2-18/+14
The commit 39bbf82d8c2b ("phy: qcom-qmp: pcs-usb: Add v6 register offsets") incorrectly added plain PCS registers to the PCS_USB header. Move them to a proper location. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-10-13phy: qcom-qmp-combo: fix the prefix for the PCS_USB v6 registersDmitry Baryshkov2-39/+39
For all other generations, we have been using just the QPHY prefix for the PCS registers. Remove the _USB part of the QPHY_USB prefix. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-10-13Merge branch 'fixes' into nextVinod Koul5-11/+29
Merge fixes into next as qmp phy patches on list depend on it
2023-09-21phy: qualcomm: phy-qcom-eusb2-repeater: Add tuning overridesKonrad Dybcio1-1/+16
There are devices in the wild, like the Sony Xperia 1 V that *require* different tuning than the base design for USB to work. Add support for overriding the necessary tuning values. Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-09-21phy: qualcomm: phy-qcom-eusb2-repeater: Zero out untouched tuning regsKonrad Dybcio1-14/+44
The vendor kernel zeroes out all tuning data outside the init sequence as part of initialization. Follow suit to avoid UB. Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-09-21phy: qualcomm: phy-qcom-eusb2-repeater: Use regmap_fieldsKonrad Dybcio1-30/+61
Switch to regmap_fields, so that the values written into registers are sanitized by their explicit sizes and the different registers are structured in an iterable object to make external changes to the init sequence simpler. Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-09-21phy: qcom-m31: Add compatible, phy init sequence for IPQ5018Nitheesh Sekar1-0/+51
Add phy init sequence and compatible string for IPQ5018 chipset. Signed-off-by: Nitheesh Sekar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-09-21phy: qualcomm: Fix typos in commentsBo Liu1-1/+1
Fix typo in the description of the 'succesfully'. Signed-off-by: Bo Liu <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-09-21phy: qcom-qmp-combo: initialize PCS_USB registersKonrad Dybcio1-0/+4
Currently, PCS_USB registers that have their initialization data in a pcs_usb_tbl table are never initialized. Fix that. Fixes: fc64623637da ("phy: qcom-qmp-combo,usb: add support for separate PCS_USB region") Reported-by: Adrien Thierry <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-09-21phy: qcom-qmp-combo: Square out 8550 POWER_STATE_CONFIG1Konrad Dybcio2-2/+3
There are two instances of the POWER_STATE_CONFIG1 register: one in the PCS space and another one in PCS_USB. The downstream init sequence pokes the latter one while we've been poking the former one (and misnamed it as the latter one, impostor!). Fix that up to avoid UB. Fixes: 49742e9edab3 ("phy: qcom-qmp-combo: Add support for SM8550") Reviewed-by: Abel Vesa <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-09-21phy: qcom: m31: Remove unwanted qphy->vreg is NULL checkVaradarajan Narayanan1-2/+1
Fix the following Smatch complaint: drivers/phy/qualcomm/phy-qcom-m31.c:175 m31usb_phy_init() warn: variable dereferenced before check 'qphy->vreg' (see line 167) drivers/phy/qualcomm/phy-qcom-m31.c 166 167 ret = regulator_enable(qphy->vreg); ^^^^^^^^^^ Unchecked dereference 168 if (ret) { 169 dev_err(&phy->dev, "failed to enable regulator, %d\n", ret); 170 return ret; 171 } 172 173 ret = clk_prepare_enable(qphy->clk); 174 if (ret) { 175 if (qphy->vreg) ^^^^^^^^^^ Checked too late 176 regulator_disable(qphy->vreg); 177 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret); Since the phy will not get registered if qphy->vreg is NULL, this check is not needed. Reported-by: Dan Carpenter <[email protected]> Closes: https://lore.kernel.org/linux-phy/[email protected]/T/#u Fixes: 08e49af50701 ("phy: qcom: Introduce M31 USB PHY driver") Signed-off-by: Varadarajan Narayanan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-09-21phy: qcom: phy-qcom-m31: change m31_ipq5332_regs to staticYang Yingliang1-1/+1
m31_ipq5332_regs is only used in phy-qcom-m31.c now, change it to static. Signed-off-by: Yang Yingliang <[email protected]> Reviewed-by: Varadarajan Narayanan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-09-21phy: qcom: phy-qcom-m31: fix wrong pointer pass to PTR_ERR()Yang Yingliang1-1/+1
It should be 'qphy->vreg' passed to PTR_ERR() when devm_regulator_get() fails. Fixes: 08e49af50701 ("phy: qcom: Introduce M31 USB PHY driver") Signed-off-by: Yang Yingliang <[email protected]> Reviewed-by: Varadarajan Narayanan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-09-21phy: qcom-qmp-usb: populate offsets configurationDmitry Baryshkov1-3/+38
Populate offsets configuration for the rest of USB PHYs to make it possible to switch them to the new (single-node) bindings style. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-09-21phy: qcom-qmp: move PCS MISC V4 registers to separate headerDmitry Baryshkov3-8/+18
Move PCS MISC V4 registers to the separate header. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-09-21phy: qcom-qmp-usb: make QPHY_PCS_MISC_CLAMP_ENABLE access conditionalDmitry Baryshkov1-5/+17
The register QPHY_V[34]_PCS_MISC_CLAMP_ENABLE is present only on some SoC families. Other platforms (qcm2290) can have PCS_MISC region, but do not have this register. Add it to the register layout table and check that it is defined before toggling CLAMP settings. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-09-21phy: qcom-qmp-usb: rework reset handlingDmitry Baryshkov1-45/+26
All legacy bindings of USB PHYs use "phy", "common" resets, while newer style bindings use "phy", "phy_phy" resets. In preparation for converting existing legacy PHY bindings to use newer scheme, drop reset lists from configuration struture and reference reset lists directly. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-09-21phy: qcom-qmp-usb: simplify clock handlingDmitry Baryshkov1-66/+24
For the existing PHYs for new binding we are going to drop ref_clk_src clock and always use ref clock. Rather than introducing additional code to handle legacy vs current bindings (and clock names), use devm_clk_bulk_get_optional() when new bindings are used and devm_clk_bulk_get_all() when legacy bindings are in place. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-09-21phy: qcom-qmp-usb: split PCS_USB init table for sc8280xp and sa8775pAdrien Thierry1-5/+15
For sc8280xp and sa8775p, PCS and PCS_USB initialization data is described in the same table, thus the pcs_usb offset is not being applied during initialization of PCS_USB registers. Fix this by adding the appropriate pcs_usb_tbl tables. Fixes: 8bd2d6e11c99 ("phy: qcom-qmp: Add SA8775P USB3 UNI phy") Fixes: c0c7769cdae2 ("phy: qcom-qmp: Add SC8280XP USB3 UNI phy") Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Adrien Thierry <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-09-21phy: qcom-qmp-usb: initialize PCS_USB registersAdrien Thierry1-0/+4
Currently, PCS_USB registers that have their initialization data in a pcs_usb_tbl table are never initialized. Fix that. Fixes: fc64623637da ("phy: qcom-qmp-combo,usb: add support for separate PCS_USB region") Signed-off-by: Adrien Thierry <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-09-21phy: qcom-qmp-ufs: Add Phy Configuration support for SC7280Nitin Rawat1-0/+142
Add SC7280 specific register layout and table configs. Co-developed-by: Manish Pandey <[email protected]> Signed-off-by: Manish Pandey <[email protected]> Signed-off-by: Nitin Rawat <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-09-21phy: qcom: m31: Fix indentation issuesVaradarajan Narayanan1-3/+3
Fix incorrect indentation Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Varadarajan Narayanan <[email protected]> Link: https://lore.kernel.org/r/7ca6fa68ba33742fcf65147c038c1102cc4901b4.1693468292.git.quic_varada@quicinc.com Signed-off-by: Vinod Koul <[email protected]>
2023-09-03Merge tag 'phy-for-6.6' of ↵Linus Torvalds22-918/+2376
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "As usual a couple of new drivers, a bunch of new device support and few updates to existing drivers New Support: - Starfive dphy rx, JH7110 usb and pcie support - Rockchip rv1126 inno-dsi phy, rk3588 usb and pcie support - Qualcomm sa8775p PCIe support, M31 USB PHY driver - Samsung Exynos850 usb support Updates: - Mediatek dsi driver clock updates - Qualcomm sm8150 combo phy with reworking of qmp pcie driver - Xilinx zynqmp runtime PM support" * tag 'phy-for-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (83 commits) phy: exynos5-usbdrd: Add Exynos850 support phy: exynos5-usbdrd: Add 26MHz ref clk support phy: exynos5-usbdrd: Make it possible to pass custom phy ops dt-bindings: phy: samsung,usb3-drd-phy: Add Exynos850 support phy: qcom-qmp-combo: fix clock probing phy: qcom-qmp-pcie: support SM8150 PCIe QMP PHYs phy: qcom-qmp-pcie: populate offsets configuration phy: qcom-qmp-pcie: simplify clock handling phy: qcom-qmp-pcie: keep offset tables sorted phy: qcom-qmp-pcie: drop ln_shrd from v5_20 config dt-bindings: phy: qcom,qmp-pcie: describe SM8150 PCIe PHYs dt-bindings: phy: migrate QMP PCIe PHY bindings to qcom,sc8280xp-qmp-pcie-phy.yaml phy: fsl-imx8mq-usb: add dev_err_probe if getting vbus failed phy: qcom: Introduce M31 USB PHY driver dt-bindings: phy: qcom,m31: Document qcom,m31 USB phy phy: rockchip: inno-dsidphy: Add rv1126 support dt-bindings: phy: rockchip-inno-dsidphy: Document rv1126 dt-bindings: phy: mediatek,tphy: allow simple nodename pattern phy: amlogic: meson-g12a-usb2: fix Wvoid-pointer-to-enum-cast warning phy: marvell pxa-usb: fix Wvoid-pointer-to-enum-cast warning ...
2023-08-30Merge tag 'clk-for-linus' of ↵Linus Torvalds1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk subsystem updates from Stephen Boyd: "This pull request is full of clk driver changes. In fact, there aren't any changes to the clk framework this time around. That's probably because everyone was on vacation (yours truly included). We did lose a couple clk drivers this time around because nobody was using those devices. That skews the diffstat a bit, but either way, nothing looks out of the ordinary here. The usual suspects are chugging along adding support for more SoCs and fixing bugs. If I had to choose, I'd say the theme for the past few months has been "polish". There's quite a few patches that migrate to devm_platform_ioremap_resource() in here. And there's more than a handful of patches that move the NR_CLKS define from the DT binding header to the driver. There's even patches that migrate drivers to use clk_parent_data and clk_hw to describe clk tree topology. It seems that the spring (summer?) cleaning bug got some folks, or the semiconductor shortage finally hit the software side. New Drivers: - StarFive JH7110 SoC clock drivers - Qualcomm IPQ5018 Global Clock Controller driver - Versa3 clk generator to support 48KHz playback/record with audio codec on RZ/G2L SMARC EVK Removed Drivers: - Remove non-OF mmp clk drivers - Remove OXNAS clk driver Updates: - Add __counted_by to struct clk_hw_onecell_data and struct spmi_pmic_div_clk_cc - Move defines for numbers of clks (NR_CLKS) from DT headers to drivers - Introduce kstrdup_and_replace() and use it - Add PLL rates for Rockchip rk3568 - Add the display clock tree for Rockchip rv1126 - Add Audio Clock Generator (ADG) clocks on Renesas R-Car Gen3 and RZ/G2 SoCs - Convert sun9i-mmc clock to use devm_platform_get_and_ioremap_resource() - Fix function name in a comment in ccu_mmc_timing.c - Parameter name correction for ccu_nkm_round_rate() - Implement CLK_SET_RATE_PARENT for Allwinner NKM clocks, i.e. consider alternative parent rates when determining clock rates - Set CLK_SET_RATE_PARENT for Allwinner A64 pll-mipi - Support finding closest (as opposed to closest but not higher) clock rate for NM, NKM, mux and div type clocks, as use it for Allwinner A64 pll-video0 - Prefer current parent rate if able to generate ideal clock rate for Allwinner NKM clocks - Clean up Qualcomm SMD RPM driver, with interconnect bus clocks moved out to the interconnect drivers - Fix various PM runtime bugs across many Qualcomm clk drivers - Migrate Qualcomm MDM9615 is to parent_hw and parent_data - Add network related resets on Qualcomm IPQ4019 - Add a couple missing USB related clocks to Qualcomm IPQ9574 - Add missing gpll0_sleep_clk_src to Qualcomm MSM8917 global clock controller - In the Qualcomm QDU1000 global clock controller, GDSCs, clkrefs, and GPLL1 are added, while PCIe pipe clock, SDCC rcg ops are corrected - Add missing GDSCs to and correct GDSCs for the SC8280XP global clock controller driver - Support retention for the Qualcomm SC8280XP display clock controller GDSCs. - Qualcommm's SDCC apps_clk_src is marked with CLK_OPS_PARENT_ENABLE to fix issues with missing parent clocks across sc7180, sm7150, sm6350 and sm8250, while sm8450 is corrected to use floor ops - Correct Qualcomm SM6350 GPU clock controller's clock supplies - Drop unwanted clocks from the Qualcomm IPQ5332 GCC driver - Add missing OXILICX GDSC to Qualcomm MSM8226 GCC - Change the delay in the Qualcomm reset controller to fsleep() for correctness - Extend the Qualcomm SM83550 Video clock controller to support SC8280XP - Add graphics clock support on Renesas RZ/G2M, RZ/G2N, RZ/G2E, and R-Car H3, M3-W, and M3-N SoCs - Add Clocked Serial Interface (CSI) clocks on Renesas RZ/V2M - Add PWM (MTU3) clock and reset on Renesas RZ/G2UL and RZ/Five - Add the PDM IPC clock for i.MX93 - Add 519.75MHz frequency support for i.MX9 PLL - Simplify the .determine_rate() implementation for i.MX GPR mux - Make the i.MX8QXP LPCG clock use devm_platform_ioremap_resource() - Add the audio mux clock to i.MX8 - Fix the SPLL2 MULT range for PLLv4 - Update the SPLL2 type in i.MX8ULP - Fix the SAI4 clock on i.MX8MP - Add silicon revision print for i.MX25 on clocks init - Drop the return value from __mx25_clocks_init() - Fix the clock pauses on no-op set_rate for i.MX8M composite clock - Drop restrictions for i.MX PLL14xx and fix its max prediv value - Drop the 393216000 and 361267200 from i.MX PLL14xx rate table to allow glitch free switching" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (207 commits) clk: qcom: Fix SM_GPUCC_8450 dependencies clk: lmk04832: Support using PLL1_LD as SPI readback pin clk: lmk04832: Don't disable vco clock on probe fail clk: lmk04832: Set missing parent_names for output clocks clk: mvebu: Convert to devm_platform_ioremap_resource() clk: nuvoton: Convert to devm_platform_ioremap_resource() clk: socfpga: agilex: Convert to devm_platform_ioremap_resource() clk: ti: Use devm_platform_get_and_ioremap_resource() clk: mediatek: Convert to devm_platform_ioremap_resource() clk: hsdk-pll: Convert to devm_platform_ioremap_resource() clk: gemini: Convert to devm_platform_ioremap_resource() clk: fsl-sai: Convert to devm_platform_ioremap_resource() clk: bm1880: Convert to devm_platform_ioremap_resource() clk: axm5516: Convert to devm_platform_ioremap_resource() clk: actions: Convert to devm_platform_ioremap_resource() clk: cdce925: Remove redundant of_match_ptr() clk: pxa910: Move number of clocks to driver source clk: pxa1928: Move number of clocks to driver source clk: pxa168: Move number of clocks to driver source clk: mmp2: Move number of clocks to driver source ...
2023-08-22clk: Annotate struct clk_hw_onecell_data with __counted_byKees Cook1-1/+1
Prepare for the coming implementation by GCC and Clang of the __counted_by attribute. Flexible array members annotated with __counted_by can have their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS (for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family functions). As found with Coccinelle[1], add __counted_by for struct clk_hw_onecell_data. Additionally, since the element count member must be set before accessing the annotated flexible array member, move its initialization earlier. [1] https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci Cc: Michael Turquette <[email protected]> Cc: Stephen Boyd <[email protected]> Cc: Joel Stanley <[email protected]> Cc: Andrew Jeffery <[email protected]> Cc: Taichi Sugaya <[email protected]> Cc: Takao Orito <[email protected]> Cc: Qin Jian <[email protected]> Cc: Andrew Lunn <[email protected]> Cc: Gregory Clement <[email protected]> Cc: Sebastian Hesselbarth <[email protected]> Cc: Andy Gross <[email protected]> Cc: Bjorn Andersson <[email protected]> Cc: Konrad Dybcio <[email protected]> Cc: Sergio Paracuellos <[email protected]> Cc: Matthias Brugger <[email protected]> Cc: AngeloGioacchino Del Regno <[email protected]> Cc: Maxime Ripard <[email protected]> Cc: Chen-Yu Tsai <[email protected]> Cc: Jernej Skrabec <[email protected]> Cc: David Airlie <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Samuel Holland <[email protected]> Cc: Vinod Koul <[email protected]> Cc: Kishon Vijay Abraham I <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Signed-off-by: Kees Cook <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Gustavo A. R. Silva <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2023-08-22phy: qcom-qmp-combo: fix clock probingDmitry Baryshkov1-6/+6
During rebase of qcom-qmp-combo series a call to devm_clk_bulk_get_all() got moved by git from qmp_combo_parse_dt_legacy() to phy_dp_clks_register(). This doesn't have any serious effect, since the clocks will be set in both legacy and non-legacy paths. However let's move it back to place anyway, to prevent the driver from fetching clocks twice. Fixes: 28e265bf84a8 ("phy: qcom-qmp-combo: simplify clock handling") Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-08-22phy: qcom-qmp-pcie: support SM8150 PCIe QMP PHYsDmitry Baryshkov1-0/+6
Reuse sm8250 configuration to add support for both single lane and dual lane PCIe PHYs on the Qualcomm SM8150 platform. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-08-22phy: qcom-qmp-pcie: populate offsets configurationDmitry Baryshkov1-0/+74
Populate offsets configuration for the rest of UFS PHYs to make it possible to switch them to the new (single-node) bindings style. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-08-22phy: qcom-qmp-pcie: simplify clock handlingDmitry Baryshkov1-71/+7
For some of existing PHYs for new binding we are going to change refgen to more correct "rchng". Rather than introducing additional code to handle legacy vs current bindings (and clock names), use devm_clk_bulk_get_optional(). Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-08-22phy: qcom-qmp-pcie: keep offset tables sortedDmitry Baryshkov1-11/+11
In order to simplify adding new PHY configurations, keep register offset structs sorted by the version. Fixes: a05b6d5135ec ("phy: qcom-qmp-pcie: add support for sa8775p") Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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