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path: root/drivers/phy/freescale/Makefile
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2024-06-15phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver supportRichard Zhu1-0/+1
Add i.MX8QM HSIO PHY driver support. i.MX8QM HSIO has three lane PHY instances, and can be bound to the following controllers in the different use cases listed in below table. - two lanes capable PCIEA controller. - one lane PCIEB controller. - AHCI SATA controller. i.MX8QM HSIO PHYs support the following use cases. +----------------------------------------------------+ | | Lane0| Lane1| Lane2| |-------------------------------|------|------|------| | use case 1: PCIEAX2SATA | PCIEA| PCIEA| SATA | |-------------------------------|------|------|------| | use case 2: PCIEAX2PCIEB | PCIEA| PCIEA| PCIEB| |-------------------------------|------|------|------| | use case 3: PCIEAPCIEBSATA | PCIEA| PCIEB| SATA | +----------------------------------------------------+ Signed-off-by: Richard Zhu <[email protected]> Reviewed-by: Frank Li <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2024-03-29phy: freescale: add Samsung HDMI PHYLucas Stach1-0/+1
This adds the driver for the Samsung HDMI PHY found on the i.MX8MP SoC. Based on downstream implementation from Sandor Yu <[email protected]>. According to the TRM, the PHY receives parallel data from the link and serializes it. It also sets the PLL clock needed for the TX serializer. Tested-by: Luca Ceresoli <[email protected]> Tested-by: Richard Leitner <[email protected]> Co-developed-by: Marco Felsch <[email protected]> Signed-off-by: Marco Felsch <[email protected]> Signed-off-by: Lucas Stach <[email protected]> Tested-by: Alexander Stein <[email protected]> Tested-by: Frieder Schrempf <[email protected]> # Kontron BL Signed-off-by: Adam Ford <[email protected]> Tested-by: Marek Vasut <[email protected]> Tested-by: Luca Ceresoli <[email protected]> Tested-by: Tommaso Merciai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-07-08phy: freescale: Add i.MX8qm Mixel LVDS PHY supportLiu Ying1-0/+1
Add Freescale i.MX8qm LVDS PHY support. The PHY IP is from Mixel, Inc. Signed-off-by: Liu Ying <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-03-14phy: add support for the Layerscape SerDes 28GIoana Ciornei1-0/+1
This patch adds a new generic PHY driver to support the Lynx 28G SerDes block found on some of the Layerscape SoCs such as LX2160A. At the moment, only the following Ethernet protocols are supported: SGMII/1000Base-X and 10GBaseR. SerDes lanes which are not running an Ethernet protocol or a currently supported Ethenet protocol will be left as it was configured through the RCW (Reset Configuration Word) at boot time. At probe time, the platform driver will read the current configuration of both PLLs found on a SerDes block and will determine what protocols are supported using that PLL. For example, if a PLL is configured to generate a clock net (frate) of 5GHz the only protocols sustained by that PLL are SGMII/1000Base-X (using a quarter of the full clock rate) and QSGMII using the full clock net frequency on the lane. On the .set_mode() callback, the PHY driver will first check if the requested operating mode (protocol) is even supported by the current PLL configuration and will error out if not. Then, the lane is reconfigured to run on the requested protocol. Signed-off-by: Ioana Ciornei <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-12-14phy: freescale: pcie: Initialize the imx8 pcie standalone phy driverRichard Zhu1-0/+1
Add the standalone i.MX8 PCIe PHY driver. Signed-off-by: Richard Zhu <[email protected]> Tested-by: Marcel Ziswiler <[email protected]> Reviewed-by: Tim Harvey <[email protected]> Tested-by: Tim Harvey <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2019-07-01Merge tag 'phy-for-5.3' of ↵Greg Kroah-Hartman1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next phy: for 5.3 *) Add a new PHY driver for Qualcomm PCIe2 PHY *) Add a new PHY driver for Mixel DPHY present in i.MX8 *) Fix Qualcomm QMP UFS PHY driver from incorrectly reporting that PHY enable failed *) Fix _BUG_ on Amlogic G12A USB3 + PCIE Combo PHY Driver due to calling a sleeping function from invalid context *) Fix WARN_ON dump on rcar-gen3-usb2 PHY driver caused due to imbalance powered flag *) Fix .cocci and sparse warnings Signed-off-by: Kishon Vijay Abraham I <[email protected]> * tag 'phy-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: phy: qcom-qmp: Raise qcom_qmp_phy_enable() polling delay phy: meson-g12a-usb3-pcie: disable locking for cr_regmap phy: Add driver for mixel mipi dphy found on NXP's i.MX8 SoCs dt-bindings: phy: Add documentation for mixel dphy dt-bindings: phy-pxa-usb: add bindings phy: renesas: rcar-gen3-usb2: fix imbalance powered flag phy: qcom-qmp: Drop useless msm8998_pciephy_cfg setting phy: qcom-qmp: Correct READY_STATUS poll break condition phy: ti: am654-serdes: Make serdes_am654_xlate() static phy: usb: phy-brcm-usb: Fix platform_no_drv_owner.cocci warnings phy: samsung: Use struct_size() in devm_kzalloc() phy: qcom: Add Qualcomm PCIe2 PHY driver dt-bindings: phy: Add binding for Qualcomm PCIe2 PHY
2019-06-21phy: Add driver for mixel mipi dphy found on NXP's i.MX8 SoCsGuido Günther1-0/+1
This adds support for the Mixel DPHY as found on i.MX8 CPUs but since this is an IP core it will likely be found on others in the future. So instead of adding this to the nwl host driver make it a generic PHY driver. The driver supports the i.MX8MQ. Support for i.MX8QM and i.MX8QXP can be added once the necessary system controller bits are in via mixel_dphy_devdata. Signed-off-by: Guido Günther <[email protected]> Co-developed-by: Robert Chiras <[email protected]> Signed-off-by: Robert Chiras <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Reviewed-by: Sam Ravnborg <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner1-0/+1
Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-12-12phy: add driver for Freescale i.MX8MQ USB3 PHYLi Jun1-0/+1
This is a cleaned up port of the downstream i.MX8MQ USB3 PHY driver. Signed-off-by: Li Jun <[email protected]> Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
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