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path: root/drivers/pci/controller/dwc/pci-layerscape-ep.c
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2024-07-09PCI: layerscape-ep: Use the generic dw_pcie_ep_linkdown() API to handle Link ↵Manivannan Sadhasivam1-1/+1
Down event Now that dw_pcie_ep_linkdown() is available, use it. This also handles the reinitialization of DWC non-sticky registers in addition to sending the notification to EPF drivers. Closes: https://lore.kernel.org/linux-pci/20240528195539.GA458945@bhelgaas Link: https://lore.kernel.org/linux-pci/[email protected] Reported-by: Bjorn Helgaas <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Frank Li <[email protected]> Reviewed-by: Niklas Cassel <[email protected]>
2024-07-09PCI: dwc: ep: Remove dw_pcie_ep_init_notify() wrapperManivannan Sadhasivam1-1/+1
Currently dw_pcie_ep_init_notify() wrapper just calls pci_epc_init_notify() directly, so this wrapper provides no benefit to the glue drivers. Remove it and call pci_epc_init_notify() directly from glue drivers. Suggested-by: Bjorn Helgaas <[email protected]> Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Siddharth Vadapalli <[email protected]> Reviewed-by: Frank Li <[email protected]> Reviewed-by: Niklas Cassel <[email protected]>
2024-04-10PCI: endpoint: Remove "core_init_notifier" flagManivannan Sadhasivam1-0/+2
"core_init_notifier" flag is set by the glue drivers requiring refclk from the host to complete the DWC core initialization. Also, those drivers will send a notification to the EPF drivers once the initialization is fully completed using the pci_epc_init_notify() API. Only then, the EPF drivers will start functioning. For the rest of the drivers generating refclk locally, EPF drivers will start functioning post binding with them. EPF drivers rely on the 'core_init_notifier' flag to differentiate between the drivers. Unfortunately, this creates two different flows for the EPF drivers. So to avoid that, let's get rid of the "core_init_notifier" flag and follow a single initialization flow for the EPF drivers. This is done by calling the dw_pcie_ep_init_notify() from all glue drivers after the completion of dw_pcie_ep_init_registers() API. This will allow all the glue drivers to send the notification to the EPF drivers once the initialization is fully completed. Only difference here is that, the drivers requiring refclk from host will send the notification once refclk is received, while others will send it during probe time itself. But this also requires the EPC core driver to deliver the notification after EPF driver bind. Because, the glue driver can send the notification before the EPF drivers bind() and in those cases the EPF drivers will miss the event. To accommodate this, EPC core is now caching the state of the EPC initialization in 'init_complete' flag and pci-ep-cfs driver sends the notification to EPF drivers based on that after each EPF driver bind. Link: https://lore.kernel.org/linux-pci/[email protected] Tested-by: Niklas Cassel <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Frank Li <[email protected]> Reviewed-by: Niklas Cassel <[email protected]>
2024-04-10PCI: dwc: ep: Call dw_pcie_ep_init_registers() API directly from all glue ↵Manivannan Sadhasivam1-0/+7
drivers Currently, dw_pcie_ep_init_registers() API is directly called by the glue drivers requiring active refclk from host. But for the other drivers, it is getting called implicitly by dw_pcie_ep_init(). This is due to the fact that this API initializes DWC EP specific registers and that requires an active refclk (either from host or generated locally by endpoint itsef). But, this causes a discrepancy among the glue drivers. So to avoid this confusion, let's call this API directly from all glue drivers irrespective of refclk dependency. Only difference here is that the drivers requiring refclk from host will call this API only after the refclk is received and other drivers without refclk dependency will call this API right after dw_pcie_ep_init(). With this change, the check for 'core_init_notifier' flag can now be dropped from dw_pcie_ep_init() API. This will also allow us to remove the 'core_init_notifier' flag completely in the later commits. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Frank Li <[email protected]> Reviewed-by: Niklas Cassel <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]>
2024-02-16PCI: endpoint: Clean up hardware description for BARsNiklas Cassel1-1/+4
The hardware description for BARs is scattered in many different variables in pci_epc_features. Some of these things are mutually exclusive, so it can create confusion over which variable that has precedence over another. Improve the situation by creating a struct pci_epc_bar_desc, and a new enum pci_epc_bar_type, and convert the endpoint controller drivers to use this more well defined format. Additionally, some endpoint controller drivers mark the BAR succeeding a "64-bit only BAR" as reserved, while some do not. By definition, a 64-bit BAR uses the succeeding BAR for the upper 32-bits, so an EPF driver cannot use a BAR succeeding a 64-bit BAR. Ensure that all endpoint controller drivers are uniform, and actually describe a reserved BAR as reserved. Signed-off-by: Niklas Cassel <[email protected]> Reviewed-by: Kishon Vijay Abraham I <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]>
2024-01-15Merge branch 'pci/irq-clean-up'Bjorn Helgaas1-5/+5
- Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX to be more explicit and match spec terminology (Bjorn Helgaas) - Use existing PCI_IRQ_INTX, PCI_IRQ_MSI, PCI_IRQ_MSIX in artpec6, cadence, designware, designware-plat, dra7xx, imx6, keembay, keystone, layerscape, mhi, ntb, qcom, rcar, rcar-gen4, rockchip, tegra194, uniphier, vntb; drop the redundant pci_epc_irq_type enum with the same values (Damien Le Moal) - Use "intx" instead of "leg" or "legacy" when describing INTx interrupts in endpoint core, endpoint tests, cadence, dra7xx, designware, dw-rockchip, dwc core, imx6, keystone, layerscape, qcom, rcar-gen4, rockchip, tegra194, uniphier, xilinx-nwl (Damien Le Moal) * pci/irq-clean-up: PCI: xilinx-nwl: Use INTX instead of legacy PCI: rockchip-host: Rename rockchip_pcie_legacy_int_handler() PCI: rockchip-ep: Use INTX instead of legacy PCI: uniphier: Use INTX instead of legacy PCI: tegra194: Use INTX instead of legacy PCI: dw-rockchip: Rename rockchip_pcie_legacy_int_handler() PCI: keystone: Use INTX instead of legacy PCI: dwc: Rename dw_pcie_ep_raise_legacy_irq() PCI: cadence: Use INTX instead of legacy PCI: dra7xx: Rename dra7xx_pcie_raise_legacy_irq() misc: pci_endpoint_test: Use INTX instead of LEGACY PCI: endpoint: Rename LEGACY to INTX in test function driver PCI: endpoint: Use INTX instead of legacy PCI: endpoint: Drop PCI_EPC_IRQ_XXX definitions PCI: Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX
2024-01-15Merge branch 'pci/controller/layerscape'Bjorn Helgaas1-8/+8
- Add suspend/resume support for Layerscape LS1043a, including software-managed PME_Turn_Off and transitions between L0, L2/L3_Ready Link states (Frank Li) * pci/controller/layerscape: PCI: layerscape: Add suspend/resume for ls1043a PCI: layerscape(ep): Rename pf_* as pf_lut_* PCI: layerscape: Add suspend/resume for ls1021a PCI: layerscape: Add function pointer for exit_from_l2()
2024-01-06PCI: dwc: Rename .func_conf_select to .get_dbi_offset in struct dw_pcie_ep_opsYoshihiro Shimoda1-3/+2
Since the struct member .func_conf_select makes the intentions behind it difficult to ascertain from its name alone, rename it to .get_dbi_offset to make the intended usage more obvious. [kwilczynski: commmit log] Suggested-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Serge Semin <[email protected]>
2024-01-06PCI: dwc: Rename .ep_init to .init in struct dw_pcie_ep_opsYoshihiro Shimoda1-1/+1
Since the name of the dw_pcie_ep_ops struct makes it obvious that it's for the PCIe Endpoint, rename the struct member .ep_init to .init. [kwilczynski: commit log] Suggested-by: Serge Semin <[email protected]> Suggested-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Serge Semin <[email protected]> Reviewed-by: Srikanth Thokala <[email protected]> Acked-by: Jesper Nilsson <[email protected]> Acked-by: Kunihiko Hayashi <[email protected]>
2023-12-19PCI: dwc: Rename dw_pcie_ep_raise_legacy_irq()Damien Le Moal1-1/+1
Rename the function dw_pcie_ep_raise_legacy_irq() of the Designware endpoint controller driver to dw_pcie_ep_raise_intx_irq() to match the name of the PCI_IRQ_INTX macro. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Damien Le Moal <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Serge Semin <[email protected]> Reviewed-by: Christoph Hellwig <[email protected]>
2023-12-18PCI: endpoint: Drop PCI_EPC_IRQ_XXX definitionsDamien Le Moal1-4/+4
linux/pci.h defines the IRQ flags PCI_IRQ_INTX, PCI_IRQ_MSI and PCI_IRQ_MSIX. Let's use these flags directly instead of the endpoint definitions provided by enum pci_epc_irq_type. This removes the need for defining this enum type completely. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Damien Le Moal <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Serge Semin <[email protected]> Reviewed-by: Christoph Hellwig <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]>
2023-12-12PCI: layerscape(ep): Rename pf_* as pf_lut_*Frank Li1-8/+8
'pf' and 'lut' are two different acronyms describing the same thing, basically it is a MMIO base address plus an offset. Rename them to avoid duplicate pf_* and lut_* naming schemes in the driver. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Frank Li <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Acked-by: Roy Zang <[email protected]>
2023-10-10PCI: layerscape-ep: Set 64-bit DMA maskGuanhua Gao1-0/+2
Set DMA mask and coherent DMA mask to enable 64-bit addressing. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Guanhua Gao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Frank Li <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Christoph Hellwig <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]> Acked-by: Roy Zang <[email protected]>
2023-08-24PCI: layerscape: Add workaround for lost link capabilities during resetXiaowei Bao1-0/+19
The endpoint controller loses the Maximum Link Width and Supported Link Speed value from the Link Capabilities Register - initially configured by the Reset Configuration Word (RCW) - during a link-down or hot reset event. Address this issue in the endpoint event handler. Link: https://lore.kernel.org/r/[email protected] Fixes: a805770d8a22 ("PCI: layerscape: Add EP mode support") Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Frank Li <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]>
2023-08-24PCI: layerscape: Add support for link-down notificationFrank Li1-0/+1
Add support to pass link-down notification to the endpoint function driver so that it can process the LINK_DOWN event. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Frank Li <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]>
2023-06-23PCI: layerscape: Add the endpoint linkup notifier supportFrank Li1-1/+99
Layerscape has PME interrupt, which can be used as linkup notifier. Set CFG_READY bit of PEX_PF0_CONFIG to enable accesses from root complex when linkup detected. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Frank Li <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]>
2023-03-17PCI: layerscape: Add EP mode support for ls1028aXiaowei Bao1-0/+1
Add PCIe EP mode support for ls1028a. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Frank Li <Frank.Li@nxp> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Alok Tiwari <[email protected]> Acked-by: Roy Zang <[email protected]>
2022-07-05PCI: dwc: Add start_link/stop_link inlinesSerge Semin1-12/+0
Factor out this pattern: if (!pci->ops || !pci->ops->start_link) return -EINVAL; return pci->ops->start_link(pci); into a new dw_pcie_start_link() wrapper and do the same for the stop_link() method. Note that dw_pcie_ep_start() previously returned -EINVAL if there was no platform start_link() method, which didn't make much sense since that is not an error. It will now return 0 in that case. As a side-effect, drop the empty start_link() and dummy dw_pcie_ops instances from the generic DW PCIe and Layerscape EP platform drivers. [bhelgaas: commit log] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
2021-03-22PCI: layerscape: Correct syntax by changing comma to semicolonKrzysztof Wilczyński1-1/+1
Replace command with a semicolon to correct syntax and to prevent potential unspecified behaviour and/or unintended side effects. Related: https://lore.kernel.org/linux-pci/[email protected]/ Co-authored-by: Zheng Yongjun <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Roy Zang <[email protected]>
2021-02-24PCI: layerscape: Add LX2160A rev2 EP mode supportHou Zhiqiang1-0/+7
The LX2160A rev2 uses the same PCIe IP as LS2088A, but LX2160A rev2 PCIe controller is integrated with different stride between PFs' register address. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2020-11-19PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common codeRob Herring1-35/+2
Most DWC drivers use the common register resource names "dbi", "dbi2", and "addr_space", so let's move their setup into the DWC common code. This means 'dbi_base' in particular is setup later, but it looks like no drivers touch DBI registers before dw_pcie_host_init or dw_pcie_ep_init. Link: https://lore.kernel.org/r/[email protected] Tested-by: Marek Szyprowski <[email protected]> Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Jingoo Han <[email protected]> Cc: Kishon Vijay Abraham I <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Murali Karicheri <[email protected]> Cc: Minghuan Lian <[email protected]> Cc: Mingkai Hu <[email protected]> Cc: Roy Zang <[email protected]> Cc: Jonathan Chocron <[email protected]> Cc: Jesper Nilsson <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Xiaowei Song <[email protected]> Cc: Binghui Wang <[email protected]> Cc: Andy Gross <[email protected]> Cc: Bjorn Andersson <[email protected]> Cc: Stanimir Varbanov <[email protected]> Cc: Pratyush Anand <[email protected]> Cc: Thierry Reding <[email protected]> Cc: Jonathan Hunter <[email protected]> Cc: Kunihiko Hayashi <[email protected]> Cc: Masahiro Yamada <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected]
2020-09-21PCI: layerscape: Add EP mode support for ls1088a and ls2088aXiaowei Bao1-19/+53
Add PCIe EP mode support for ls1088a and ls2088a, there are some difference between LS1 and LS2 platform, so refactor the code of the EP driver. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2020-09-21PCI: layerscape: Modify the MSIX to the doorbell modeXiaowei Bao1-1/+2
dw_pcie_ep_raise_msix_irq was never called in the exisitng driver before, because the ls1046a platform don't support the MSIX feature and msix_capable was always set to false. Now that add the ls1088a platform with MSIX support, use the doorbell method to support the MSIX feature. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]>
2020-09-21PCI: layerscape: Modify the way of getting capability with different PEXXiaowei Bao1-8/+23
The different PCIe controller in one board may be have different capability of MSI or MSIX, so change the way of getting the MSI capability, make it more flexible. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2020-09-21PCI: layerscape: Fix some format issue of the codeXiaowei Bao1-2/+2
Fix some format issue of the code in EP driver. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]>
2019-10-14PCI: Add PCI_STD_NUM_BARS for the number of standard BARsDenis Efremov1-1/+1
Code that iterates over all standard PCI BARs typically uses PCI_STD_RESOURCE_END. However, that requires the unusual test "i <= PCI_STD_RESOURCE_END" rather than something the typical "i < PCI_STD_NUM_BARS". Add a definition for PCI_STD_NUM_BARS and change loops to use the more idiomatic C style to help avoid fencepost errors. Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Denis Efremov <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Sebastian Ott <[email protected]> # arch/s390/ Acked-by: Bartlomiej Zolnierkiewicz <[email protected]> # video/fbdev/ Acked-by: Gustavo Pimentel <[email protected]> # pci/controller/dwc/ Acked-by: Jack Wang <[email protected]> # scsi/pm8001/ Acked-by: Martin K. Petersen <[email protected]> # scsi/pm8001/ Acked-by: Ulf Hansson <[email protected]> # memstick/
2019-08-14PCI: layerscape: Add the bar_fixed_64bit property to the endpoint driverXiaowei Bao1-0/+1
The layerscape PCIe controller have 4 BARs. BAR0 and BAR1 are 32bit, BAR2 and BAR4 are 64bit and that's a fixed hardware configuration. Set the bar_fixed_64bit variable accordingly. Signed-off-by: Xiaowei Bao <[email protected]> [[email protected]: commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Kishon Vijay Abraham I <[email protected]>
2019-04-15PCI: dwc: Add const qualifier to struct dw_pcie_ep_opsKishon Vijay Abraham I1-1/+1
Add const qualifier to struct dw_pcie_ep_ops member of struct dw_pcie_ep. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2019-02-21PCI: layerscape: Add EP mode supportXiaowei Bao1-0/+156
Add the PCIe EP mode support to the layerscape platform controller. Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Minghuan Lian <[email protected]> Reviewed-by: Zhiqiang Hou <[email protected]> Reviewed-by: Kishon Vijay Abraham I <[email protected]>
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