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path: root/drivers/pci/controller/dwc/pci-layerscape-ep.c
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2023-03-17PCI: layerscape: Add EP mode support for ls1028aXiaowei Bao1-0/+1
Add PCIe EP mode support for ls1028a. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Frank Li <Frank.Li@nxp> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Alok Tiwari <[email protected]> Acked-by: Roy Zang <[email protected]>
2022-07-05PCI: dwc: Add start_link/stop_link inlinesSerge Semin1-12/+0
Factor out this pattern: if (!pci->ops || !pci->ops->start_link) return -EINVAL; return pci->ops->start_link(pci); into a new dw_pcie_start_link() wrapper and do the same for the stop_link() method. Note that dw_pcie_ep_start() previously returned -EINVAL if there was no platform start_link() method, which didn't make much sense since that is not an error. It will now return 0 in that case. As a side-effect, drop the empty start_link() and dummy dw_pcie_ops instances from the generic DW PCIe and Layerscape EP platform drivers. [bhelgaas: commit log] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
2021-03-22PCI: layerscape: Correct syntax by changing comma to semicolonKrzysztof Wilczyński1-1/+1
Replace command with a semicolon to correct syntax and to prevent potential unspecified behaviour and/or unintended side effects. Related: https://lore.kernel.org/linux-pci/[email protected]/ Co-authored-by: Zheng Yongjun <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Roy Zang <[email protected]>
2021-02-24PCI: layerscape: Add LX2160A rev2 EP mode supportHou Zhiqiang1-0/+7
The LX2160A rev2 uses the same PCIe IP as LS2088A, but LX2160A rev2 PCIe controller is integrated with different stride between PFs' register address. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2020-11-19PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common codeRob Herring1-35/+2
Most DWC drivers use the common register resource names "dbi", "dbi2", and "addr_space", so let's move their setup into the DWC common code. This means 'dbi_base' in particular is setup later, but it looks like no drivers touch DBI registers before dw_pcie_host_init or dw_pcie_ep_init. Link: https://lore.kernel.org/r/[email protected] Tested-by: Marek Szyprowski <[email protected]> Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Jingoo Han <[email protected]> Cc: Kishon Vijay Abraham I <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Murali Karicheri <[email protected]> Cc: Minghuan Lian <[email protected]> Cc: Mingkai Hu <[email protected]> Cc: Roy Zang <[email protected]> Cc: Jonathan Chocron <[email protected]> Cc: Jesper Nilsson <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Xiaowei Song <[email protected]> Cc: Binghui Wang <[email protected]> Cc: Andy Gross <[email protected]> Cc: Bjorn Andersson <[email protected]> Cc: Stanimir Varbanov <[email protected]> Cc: Pratyush Anand <[email protected]> Cc: Thierry Reding <[email protected]> Cc: Jonathan Hunter <[email protected]> Cc: Kunihiko Hayashi <[email protected]> Cc: Masahiro Yamada <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected]
2020-09-21PCI: layerscape: Add EP mode support for ls1088a and ls2088aXiaowei Bao1-19/+53
Add PCIe EP mode support for ls1088a and ls2088a, there are some difference between LS1 and LS2 platform, so refactor the code of the EP driver. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2020-09-21PCI: layerscape: Modify the MSIX to the doorbell modeXiaowei Bao1-1/+2
dw_pcie_ep_raise_msix_irq was never called in the exisitng driver before, because the ls1046a platform don't support the MSIX feature and msix_capable was always set to false. Now that add the ls1088a platform with MSIX support, use the doorbell method to support the MSIX feature. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]>
2020-09-21PCI: layerscape: Modify the way of getting capability with different PEXXiaowei Bao1-8/+23
The different PCIe controller in one board may be have different capability of MSI or MSIX, so change the way of getting the MSI capability, make it more flexible. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2020-09-21PCI: layerscape: Fix some format issue of the codeXiaowei Bao1-2/+2
Fix some format issue of the code in EP driver. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]>
2019-10-14PCI: Add PCI_STD_NUM_BARS for the number of standard BARsDenis Efremov1-1/+1
Code that iterates over all standard PCI BARs typically uses PCI_STD_RESOURCE_END. However, that requires the unusual test "i <= PCI_STD_RESOURCE_END" rather than something the typical "i < PCI_STD_NUM_BARS". Add a definition for PCI_STD_NUM_BARS and change loops to use the more idiomatic C style to help avoid fencepost errors. Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Denis Efremov <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Sebastian Ott <[email protected]> # arch/s390/ Acked-by: Bartlomiej Zolnierkiewicz <[email protected]> # video/fbdev/ Acked-by: Gustavo Pimentel <[email protected]> # pci/controller/dwc/ Acked-by: Jack Wang <[email protected]> # scsi/pm8001/ Acked-by: Martin K. Petersen <[email protected]> # scsi/pm8001/ Acked-by: Ulf Hansson <[email protected]> # memstick/
2019-08-14PCI: layerscape: Add the bar_fixed_64bit property to the endpoint driverXiaowei Bao1-0/+1
The layerscape PCIe controller have 4 BARs. BAR0 and BAR1 are 32bit, BAR2 and BAR4 are 64bit and that's a fixed hardware configuration. Set the bar_fixed_64bit variable accordingly. Signed-off-by: Xiaowei Bao <[email protected]> [[email protected]: commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Kishon Vijay Abraham I <[email protected]>
2019-04-15PCI: dwc: Add const qualifier to struct dw_pcie_ep_opsKishon Vijay Abraham I1-1/+1
Add const qualifier to struct dw_pcie_ep_ops member of struct dw_pcie_ep. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2019-02-21PCI: layerscape: Add EP mode supportXiaowei Bao1-0/+156
Add the PCIe EP mode support to the layerscape platform controller. Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Minghuan Lian <[email protected]> Reviewed-by: Zhiqiang Hou <[email protected]> Reviewed-by: Kishon Vijay Abraham I <[email protected]>
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