aboutsummaryrefslogtreecommitdiff
path: root/drivers/pci/controller/cadence
AgeCommit message (Collapse)AuthorFilesLines
2024-09-19Merge branch 'pci/misc'Bjorn Helgaas1-1/+1
- Check pcie_find_root_port() return in x86 fixups to avoid NULL pointer dereferences (Samasth Norway Ananda) - Make pci_bus_type constant (Kunwu Chan) - Remove unused declarations of __pci_pme_wakeup() and pci_vpd_release() (Yue Haibing) - Remove any leftover .*.cmd files with make clean (zhang jiao) * pci/misc: PCI: Fix typos PCI/VPD: Remove pci_vpd_release() unused declarations PCI/PM: Remove __pci_pme_wakeup() unused declarations PCI: Make pci_bus_type constant x86/PCI: Check pcie_find_root_port() return for NULL
2024-09-19Merge branch 'pci/controller/j721e'Bjorn Helgaas3-35/+181
- Add DT "ti,syscon-acspcie-proxy-ctrl" and driver support to enable the ACSPCIE module to drive Refclk for the Endpoint (Siddharth Vadapalli) - Extract the cadence link setup from cdns_pcie_host_setup() so link setup can be done separately during resume (Thomas Richard) - Use dev_err_probe() to simplify j721e probe (Thomas Richard) - Add T_PERST_CLK_US definition for the mandatory delay between Refclk becoming stable and PERST# being deasserted (Thomas Richard) - Add j721e suspend and resume support (Théo Lebrun) * pci/controller/j721e: PCI: j721e: Add suspend and resume support PCI: j721e: Use T_PERST_CLK_US macro PCI: Add T_PERST_CLK_US macro PCI: j721e: Add reset GPIO to struct j721e_pcie PCI: j721e: Use dev_err_probe() in the probe() function PCI: cadence: Set cdns_pcie_host_init() global PCI: cadence: Extract link setup sequence from cdns_pcie_host_setup() PCI: j721e: Enable ACSPCIE Refclk if "ti,syscon-acspcie-proxy-ctrl" exists dt-bindings: PCI: ti,j721e-pci-host: Add ACSPCIE proxy control property
2024-09-19PCI: Fix typosBjorn Helgaas1-1/+1
Fix typos. Signed-off-by: Bjorn Helgaas <[email protected]>
2024-09-04PCI: j721e: Add suspend and resume supportThéo Lebrun1-6/+92
Add suspend and resume support. Only the Root Complex mode is supported. During the suspend stage PERST# is asserted, then deasserted during the resume stage. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Théo Lebrun <[email protected]> Signed-off-by: Thomas Richard <[email protected]> [kwilczynski: commit log, update references to the PCI SIG specification] Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Siddharth Vadapalli <[email protected]>
2024-09-04PCI: j721e: Use T_PERST_CLK_US macroThomas Richard1-1/+1
Use the T_PERST_CLK_US macro, and the fsleep() function instead of usleep_range(). Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Thomas Richard <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]>
2024-09-03PCI: cadence: Drop excess cdns_pcie_rc.dev kerneldoc descriptionBjorn Helgaas1-1/+0
Struct cdns_pcie_rc once had a .dev member, but it was removed by bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library"). Drop the extra kerneldoc for it. Signed-off-by: Bjorn Helgaas <[email protected]>
2024-09-03PCI: j721e: Add reset GPIO to struct j721e_pcieThéo Lebrun1-0/+2
Add reset GPIO to struct j721e_pcie, so it can be used at suspend and resume stages. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Théo Lebrun <[email protected]> Signed-off-by: Thomas Richard <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]>
2024-09-03PCI: j721e: Use dev_err_probe() in the probe() functionThomas Richard1-11/+8
Use dev_err_probe() instead of dev_err() in the probe() function to simplify the code and standardize the error output. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Thomas Richard <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Francesco Dolcini <[email protected]>
2024-09-03PCI: cadence: Set cdns_pcie_host_init() globalThomas Richard2-3/+8
During the resume sequence of the host, cdns_pcie_host_init() needs to be called, so set it global. The dev function parameter is removed, as it isn't used. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Thomas Richard <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Siddharth Vadapalli <[email protected]>
2024-09-03PCI: cadence: Extract link setup sequence from cdns_pcie_host_setup()Thomas Richard2-13/+32
The function cdns_pcie_host_setup() mixes probe structure and link setup. The link setup must be done during the resume sequence. So extract it from cdns_pcie_host_setup() and create a dedicated function. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Thomas Richard <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Siddharth Vadapalli <[email protected]>
2024-08-31PCI: j721e: Enable ACSPCIE Refclk if "ti,syscon-acspcie-proxy-ctrl" existsSiddharth Vadapalli1-1/+38
The ACSPCIE module is capable of driving the reference clock required by the PCIe Endpoint device. It is an alternative to on-board and external reference clock generators. Enabling the output from the ACSPCIE module's PAD IO Buffers requires clearing the "PAD IO disable" bits of the ACSPCIE_PROXY_CTRL register in the CTRL_MMR register space. Add support to enable the ACSPCIE reference clock output using the optional device-tree property "ti,syscon-acspcie-proxy-ctrl". Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Siddharth Vadapalli <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
2024-05-16Merge branch 'pci/controller/dwc'Bjorn Helgaas1-0/+2
- Move DBI accesses from dw_pcie_ep_init() to dw_pcie_ep_init_complete() so drivers for endpoints that require Refclk for DBI access, e.g., qcom and tegra194, can control when this happens (Manivannan Sadhasivam) - Add endpoint API kernel-doc (Manivannan Sadhasivam) - Remove .deinit() callback and instead call rcar_gen4_pcie_ep_deinit() explicitly from rcar-gen4, which was the only user (Manivannan Sadhasivam) - Rename dw_pcie_ep_exit() to dw_pcie_ep_deinit() to correspond with dw_pcie_ep_init() (Manivannan Sadhasivam) - Add dw_pcie_ep_cleanup() for drivers that need to clean up eDMA resources when PERST# is asserted, e.g., qcom, tegra194 (Manivannan Sadhasivam) - Rename dw_pcie_ep_init_complete() to dw_pcie_ep_init_registers() to better reflect the functionality (Manivannan Sadhasivam) - Call dw_pcie_ep_init_registers() directly from drivers instead of from dw_pcie_ep_init() so drivers, e.g., qcom and tegra194, can do it when Refclk is available (Manivannan Sadhasivam) - Remove the "core_init_notifier" flag, which previously identified drivers that required Refclk before DBI access, because it's now unnecessary (Manivannan Sadhasivam) * pci/controller/dwc: PCI: endpoint: Remove "core_init_notifier" flag PCI: dwc: ep: Call dw_pcie_ep_init_registers() API directly from all glue drivers PCI: dwc: ep: Rename dw_pcie_ep_init_complete() to dw_pcie_ep_init_registers() PCI: dwc: ep: Introduce dw_pcie_ep_cleanup() API for drivers supporting PERST# PCI: dwc: ep: Rename dw_pcie_ep_exit() to dw_pcie_ep_deinit() PCI: dwc: ep: Remove deinit() callback from struct dw_pcie_ep_ops PCI: dwc: ep: Add Kernel-doc comments for APIs PCI: dwc: ep: Fix DBI access failure for drivers requiring refclk from host
2024-04-10PCI: endpoint: Remove "core_init_notifier" flagManivannan Sadhasivam1-0/+2
"core_init_notifier" flag is set by the glue drivers requiring refclk from the host to complete the DWC core initialization. Also, those drivers will send a notification to the EPF drivers once the initialization is fully completed using the pci_epc_init_notify() API. Only then, the EPF drivers will start functioning. For the rest of the drivers generating refclk locally, EPF drivers will start functioning post binding with them. EPF drivers rely on the 'core_init_notifier' flag to differentiate between the drivers. Unfortunately, this creates two different flows for the EPF drivers. So to avoid that, let's get rid of the "core_init_notifier" flag and follow a single initialization flow for the EPF drivers. This is done by calling the dw_pcie_ep_init_notify() from all glue drivers after the completion of dw_pcie_ep_init_registers() API. This will allow all the glue drivers to send the notification to the EPF drivers once the initialization is fully completed. Only difference here is that, the drivers requiring refclk from host will send the notification once refclk is received, while others will send it during probe time itself. But this also requires the EPC core driver to deliver the notification after EPF driver bind. Because, the glue driver can send the notification before the EPF drivers bind() and in those cases the EPF drivers will miss the event. To accommodate this, EPC core is now caching the state of the EPC initialization in 'init_complete' flag and pci-ep-cfs driver sends the notification to EPF drivers based on that after each EPF driver bind. Link: https://lore.kernel.org/linux-pci/[email protected] Tested-by: Niklas Cassel <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Frank Li <[email protected]> Reviewed-by: Niklas Cassel <[email protected]>
2024-04-10PCI: cadence: Set a 64-bit BAR if requestedNiklas Cassel1-4/+1
Ever since commit f25b5fae29d4 ("PCI: endpoint: Setting a BAR size > 4 GB is invalid if 64-bit flag is not set") it has been impossible to get the .set_bar() callback with a BAR size > 2 GB (yes, 2GB!), if the BAR was also not requested to be configured as a 64-bit BAR. Thus, forcing setting the 64-bit flag for BARs larger than 2 GB in the lower level driver is dead code and can be removed. It is however possible that an EPF driver configures a BAR as 64-bit, even if the requested size is < 4 GB. Respect the requested BAR configuration, just like how it is already respected with regards to the prefetchable bit. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Niklas Cassel <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
2024-03-10PCI: cadence: Clear the ARI Capability Next Function Number of the last functionJasko-EXT Wojciech2-1/+19
Next Function Number field in ARI Capability Register for last function must be zero by default as per the PCIe specification, indicating there is no next higher number function but that's not happening in our case, so this patch clears the Next Function Number field for last function used. [kwilczynski: white spaces update for one define] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Jasko-EXT Wojciech <[email protected]> Signed-off-by: Achal Verma <[email protected]> Signed-off-by: Siddharth Vadapalli <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Vignesh Raghavendra <[email protected]>
2024-01-15Merge branch 'pci/irq-clean-up'Bjorn Helgaas2-16/+15
- Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX to be more explicit and match spec terminology (Bjorn Helgaas) - Use existing PCI_IRQ_INTX, PCI_IRQ_MSI, PCI_IRQ_MSIX in artpec6, cadence, designware, designware-plat, dra7xx, imx6, keembay, keystone, layerscape, mhi, ntb, qcom, rcar, rcar-gen4, rockchip, tegra194, uniphier, vntb; drop the redundant pci_epc_irq_type enum with the same values (Damien Le Moal) - Use "intx" instead of "leg" or "legacy" when describing INTx interrupts in endpoint core, endpoint tests, cadence, dra7xx, designware, dw-rockchip, dwc core, imx6, keystone, layerscape, qcom, rcar-gen4, rockchip, tegra194, uniphier, xilinx-nwl (Damien Le Moal) * pci/irq-clean-up: PCI: xilinx-nwl: Use INTX instead of legacy PCI: rockchip-host: Rename rockchip_pcie_legacy_int_handler() PCI: rockchip-ep: Use INTX instead of legacy PCI: uniphier: Use INTX instead of legacy PCI: tegra194: Use INTX instead of legacy PCI: dw-rockchip: Rename rockchip_pcie_legacy_int_handler() PCI: keystone: Use INTX instead of legacy PCI: dwc: Rename dw_pcie_ep_raise_legacy_irq() PCI: cadence: Use INTX instead of legacy PCI: dra7xx: Rename dra7xx_pcie_raise_legacy_irq() misc: pci_endpoint_test: Use INTX instead of LEGACY PCI: endpoint: Rename LEGACY to INTX in test function driver PCI: endpoint: Use INTX instead of legacy PCI: endpoint: Drop PCI_EPC_IRQ_XXX definitions PCI: Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX
2024-01-06PCI: j721e: Make TI J721E depend on ARCH_K3Peter Robinson1-0/+2
The J721E PCIe is hardware specific to TI SoC parts so add a dependency on that so it's available for those SoC parts and for compile testing but not necessarily everyone who enables the Cadence PCIe controller. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Peter Robinson <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]>
2024-01-06PCI: j721e: Add TI J784S4 PCIe configurationMatt Ranostay1-0/+22
Add PCIe configuration for J784S4 SoC platform which has 4x lane support. Link: https://lore.kernel.org/linux-pci/[email protected] Tested-by: Achal Verma <[email protected]> Signed-off-by: Matt Ranostay <[email protected]> Signed-off-by: Achal Verma <[email protected]> Signed-off-by: Siddharth Vadapalli <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Roger Quadros <[email protected]>
2023-12-19PCI: cadence: Use INTX instead of legacyDamien Le Moal2-11/+11
In the Cadence endpoint controller driver, rename the function cdns_pcie_ep_send_legacy_irq() to cdns_pcie_ep_send_intx_irq() to match the macro PCI_IRQ_INTX name. Related comments and messages mentioning "legacy" are also changed to refer to "intx". Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Damien Le Moal <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Christoph Hellwig <[email protected]>
2023-12-18PCI: endpoint: Drop PCI_EPC_IRQ_XXX definitionsDamien Le Moal1-5/+4
linux/pci.h defines the IRQ flags PCI_IRQ_INTX, PCI_IRQ_MSI and PCI_IRQ_MSIX. Let's use these flags directly instead of the endpoint definitions provided by enum pci_epc_irq_type. This removes the need for defining this enum type completely. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Damien Le Moal <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Serge Semin <[email protected]> Reviewed-by: Christoph Hellwig <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]>
2023-12-13PCI: j721e: Add PCIe 4x lane selection supportMatt Ranostay1-2/+8
Add support for setting of two-bit field that allows selection of 4x lane PCIe which was previously limited to only 2x lanes. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Matt Ranostay <[email protected]> Signed-off-by: Achal Verma <[email protected]> Signed-off-by: Siddharth Vadapalli <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Vignesh Raghavendra <[email protected]> Reviewed-by: Roger Quadros <[email protected]>
2023-12-13PCI: j721e: Add per platform maximum lane settingsMatt Ranostay1-3/+10
Various platforms have different maximum amount of lanes that can be selected. Add max_lanes to struct j721e_pcie to allow for detection of this which is needed to calculate the needed bitmask size for the possible lane count. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Matt Ranostay <[email protected]> Signed-off-by: Achal Verma <[email protected]> Signed-off-by: Siddharth Vadapalli <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Ravi Gunasekaran <[email protected]>
2023-10-28Merge branch 'pci/field-get'Bjorn Helgaas1-4/+5
- Use FIELD_GET()/FIELD_PREP() when possible throughout drivers/pci/ (Ilpo Järvinen, Bjorn Helgaas) - Rework DPC control programming for clarity (Ilpo Järvinen) * pci/field-get: PCI/portdrv: Use FIELD_GET() PCI/VC: Use FIELD_GET() PCI/PTM: Use FIELD_GET() PCI/PME: Use FIELD_GET() PCI/ATS: Use FIELD_GET() PCI/ATS: Show PASID Capability register width in bitmasks PCI: Use FIELD_GET() in Sapphire RX 5600 XT Pulse quirk PCI: Use FIELD_GET() PCI/MSI: Use FIELD_GET/PREP() PCI/DPC: Use defines with DPC reason fields PCI/DPC: Use defined fields with DPC_CTL register PCI/DPC: Use FIELD_GET() PCI: hotplug: Use FIELD_GET/PREP() PCI: dwc: Use FIELD_GET/PREP() PCI: cadence: Use FIELD_GET() PCI: Use FIELD_GET() to extract Link Width PCI: mvebu: Use FIELD_PREP() with Link Width PCI: tegra194: Use FIELD_GET()/FIELD_PREP() with Link Width fields # Conflicts: # drivers/pci/controller/dwc/pcie-tegra194.c
2023-10-18PCI: cadence: Use FIELD_GET()Ilpo Järvinen1-4/+5
Convert open-coded variants of PCI field access into FIELD_GET() to make the code easier to understand. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ilpo Järvinen <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2023-10-05PCI: cadence: Drop unused member from struct cdns_plat_pcieLi Chen1-5/+0
The struct cdns_plat_pcie contains a member called is_rc that is not being used beyond being assigned a value within the cdns_plat_pcie_probe() function, which is then not used for anything. Thus, drop is_rc from the struct cdns_plat_pcie, especially since there already is an is_rc member within the struct cdns_plat_pcie_of_data that is actively used to convey information about the PCIe controller mode. [kwilczynski: commit log] Signed-off-by: Li Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2023-08-25PCI: Fix typos in docs and commentsBjorn Helgaas1-1/+1
Fix typos in docs and comments. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Randy Dunlap <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]>
2023-07-18PCI: Explicitly include correct DT includesRob Herring3-3/+3
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2023-06-26Merge branch 'pci/controller/remove-void-callbacks'Bjorn Helgaas1-4/+2
- Convert platform_device .remove() callbacks to return void instead of a mostly useless int (Uwe Kleine-König) * pci/controller/remove-void-callbacks: PCI: xgene-msi: Convert to platform remove callback returning void PCI: tegra: Convert to platform remove callback returning void PCI: rockchip-host: Convert to platform remove callback returning void PCI: mvebu: Convert to platform remove callback returning void PCI: mt7621: Convert to platform remove callback returning void PCI: mediatek-gen3: Convert to platform remove callback returning void PCI: mediatek: Convert to platform remove callback returning void PCI: iproc: Convert to platform remove callback returning void PCI: hisi-error: Convert to platform remove callback returning void PCI: dwc: Convert to platform remove callback returning void PCI: j721e: Convert to platform remove callback returning void PCI: brcmstb: Convert to platform remove callback returning void PCI: altera-msi: Convert to platform remove callback returning void PCI: altera: Convert to platform remove callback returning void PCI: aardvark: Convert to platform remove callback returning void
2023-06-24PCI: j721e: Convert to platform remove callback returning voidUwe Kleine-König1-4/+2
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Uwe Kleine-König <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]>
2023-05-08PCI: cadence: Fix Gen2 Link Retraining processSiddharth Vadapalli1-0/+27
The Link Retraining process is initiated to account for the Gen2 defect in the Cadence PCIe controller in J721E SoC. The errata corresponding to this is i2085, documented at: https://www.ti.com/lit/er/sprz455c/sprz455c.pdf The existing workaround implemented for the errata waits for the Data Link initialization to complete and assumes that the link retraining process at the Physical Layer has completed. However, it is possible that the Physical Layer training might be ongoing as indicated by the PCI_EXP_LNKSTA_LT bit in the PCI_EXP_LNKSTA register. Fix the existing workaround, to ensure that the Physical Layer training has also completed, in addition to the Data Link initialization. Link: https://lore.kernel.org/r/[email protected] Fixes: 4740b969aaf5 ("PCI: cadence: Retrain Link to work around Gen2 training defect") Signed-off-by: Siddharth Vadapalli <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Vignesh Raghavendra <[email protected]>
2023-04-20PCI: Use consistent controller Kconfig menu entry languageBjorn Helgaas1-5/+5
Use "PCIe controller" consistently instead of "host bridge", "bus driver", etc. Annotate with "(host mode)" or "(endpoint mode)" as needed. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Helgaas <[email protected]>
2022-11-10PCI: Remove unnecessary <linux/of_irq.h> includesBjorn Helgaas1-1/+0
Many host controller drivers #include <linux/of_irq.h> even though they don't need it. Remove the unnecessary #includes. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Roy Zang <[email protected]>
2022-07-27PCI: Convert to new *_PM_OPS macrosBjorn Helgaas1-4/+2
Replace SET_*_PM_OPS with *_PM_OPS, which which have the advantage that the compiler always sees the PM callbacks as referenced, so they don't need to be wrapped with "#ifdef CONFIG_PM_SLEEP" or tagged with "__maybe_unused" to avoid "defined but not used" warnings. See 1a3c7bb08826 ("PM: core: Add new *_PM_OPS macros, deprecate old ones"). Link: https://lore.kernel.org/r/[email protected] Tested-by: Arnd Bergmann <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Pali Rohár <[email protected]> # pci-mvebu.c Reviewed-by: Arnd Bergmann <[email protected]>
2022-05-12PCI: cadence: Clear FLR in device capabilities registerParshuram Thombare3-1/+23
Clear FLR (Function Level Reset) from device capabilities registers for all physical functions. During FLR, the Margining Lane Status and Margining Lane Control registers should not be reset, as per PCIe specification. However, the controller incorrectly resets these registers upon FLR. This causes PCISIG compliance FLR test to fail. Hence preventing all functions from advertising FLR support if flag quirk_disable_flr is set. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Parshuram Thombare <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-05-12PCI: cadence: Allow PTM Responder to be enabledChristian Gmeiner2-0/+14
This enables the Controller [RP] to automatically respond with Response/ResponseD messages if CDNS_PCIE_LM_TPM_CTRL_PTMRSEN and PCI_PTM_CTRL_ENABLE bits are both set. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Christian Gmeiner <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-04-08PCI: cadence: Fix find_first_zero_bit() limitDan Carpenter1-2/+1
The ep->ob_region_map bitmap is a long and it has BITS_PER_LONG bits. Link: https://lore.kernel.org/r/20220315065829.GA13572@kili Fixes: 37dddf14f1ae ("PCI: cadence: Add EndPoint Controller driver for Cadence PCIe controller") Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-02-01PCI: j721e: Initialize pcie->cdns_pcie before using itBjorn Helgaas1-43/+42
Christian reported a NULL pointer dereference in j721e_pcie_probe() caused by 19e863828acf ("PCI: j721e: Drop redundant struct device *"), which removed struct j721e_pcie.dev since there's another copy in struct cdns_pcie.dev reachable via j721e_pcie->cdns_pcie->dev. The problem is that j721e_pcie->cdns_pcie was dereferenced before being initialized: j721e_pcie_probe pcie = devm_kzalloc() # struct j721e_pcie j721e_pcie_ctrl_init(pcie) dev = pcie->cdns_pcie->dev <-- dereference cdns_pcie switch (mode) { case PCI_MODE_RC: cdns_pcie = ... # alloc as part of pci_host_bridge pcie->cdns_pcie = cdns_pcie <-- initialize pcie->cdns_pcie Move the cdns_pcie initialization earlier so it is done before it is used. This also simplifies the error exits. Fixes: 19e863828acf ("PCI: j721e: Drop redundant struct device *") Link: https://lore.kernel.org/r/20220127222951.GA144828@bhelgaas Link: https://lore.kernel.org/r/[email protected] Reported-by: Christian Gmeiner <[email protected]> Tested-by: Christian Gmeiner <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-01-13Merge branch 'pci/driver-cleanup'Bjorn Helgaas2-14/+10
- Use of_device_get_match_data(), not of_match_device(), when we only need the device data in altera, artpec6, cadence, designware-plat, dra7xx, keystone, kirin (Fan Fei) - Drop pointless of_device_get_match_data() cast in j721e (Bjorn Helgaas) - Drop redundant struct device * from j721e since struct cdns_pcie already has one (Bjorn Helgaas) - Rename driver structs to *_pcie in intel-gw, iproc, ls-gen4, mediatek-gen3, microchip, mt7621, rcar-gen2, tegra194, uniphier, xgene, xilinx, xilinx-cpm for consistency across drivers (Fan Fei) - Fix invalid address space conversions in hisi, spear13xx (Bjorn Helgaas) * pci/driver-cleanup: PCI: spear13xx: Avoid invalid address space conversions PCI: hisi: Avoid invalid address space conversions PCI: xilinx-cpm: Rename xilinx_cpm_pcie_port to xilinx_cpm_pcie PCI: xilinx: Rename xilinx_pcie_port to xilinx_pcie PCI: xgene: Rename xgene_pcie_port to xgene_pcie PCI: uniphier: Rename uniphier_pcie_priv to uniphier_pcie PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie PCI: rcar-gen2: Rename rcar_pci_priv to rcar_pci PCI: mt7621: Rename mt7621_pci_ to mt7621_pcie_ PCI: microchip: Rename mc_port to mc_pcie PCI: mediatek-gen3: Rename mtk_pcie_port to mtk_gen3_pcie PCI: ls-gen4: Rename ls_pcie_g4 to ls_g4_pcie PCI: iproc: Rename iproc_pcie_pltfm_ to iproc_pltfm_pcie_ PCI: iproc: Rename iproc_pcie_bcma_ to iproc_bcma_pcie_ PCI: intel-gw: Rename intel_pcie_port to intel_pcie PCI: j721e: Drop redundant struct device * PCI: j721e: Drop pointless of_device_get_match_data() cast PCI: kirin: Prefer of_device_get_match_data() PCI: keystone: Prefer of_device_get_match_data() PCI: dra7xx: Prefer of_device_get_match_data() PCI: designware-plat: Prefer of_device_get_match_data() PCI: cadence: Prefer of_device_get_match_data() PCI: artpec6: Prefer of_device_get_match_data() PCI: altera: Prefer of_device_get_match_data() # Conflicts: # drivers/pci/controller/pcie-mt7621.c
2022-01-07PCI: Correct misspelled wordsKrzysztof Wilczyński1-1/+1
Fix a number of misspelled words, and while at it, correct two phrases used to indicate a status of an operation where words used have been cleverly truncated and thus always trigger a spellchecking error while performing a static code analysis over the PCI tree. [bhelgaas: reverse sense of quirk ternary] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-01-03PCI: j721e: Drop redundant struct device *Bjorn Helgaas1-8/+6
The struct cdns_pcie already contains the struct device for the j721e PCIe controller. There's no need to store another copy in struct j721e_pcie. Remove the redundant copy from struct j721e_pcie. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Helgaas <[email protected]> Cc: Kishon Vijay Abraham I <[email protected]> Cc: Tom Joseph <[email protected]>
2022-01-03PCI: j721e: Drop pointless of_device_get_match_data() castBjorn Helgaas1-2/+2
of_device_get_match_data() returns "void *", so no cast is needed when assigning the result to a pointer type. Drop the unnecessary cast. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Helgaas <[email protected]> Cc: Kishon Vijay Abraham I <[email protected]> Cc: Tom Joseph <[email protected]>
2022-01-03PCI: cadence: Prefer of_device_get_match_data()Fan Fei1-4/+2
The cadence driver only needs the device data, not the whole struct of_device_id. Use of_device_get_match_data() instead of of_match_device(). No functional change intended. [bhelgaas: commit log] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Fan Fei <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Cc: Tom Joseph <[email protected]>
2021-11-03PCI: cadence: Add cdns_plat_pcie_probe() missing returnLi Chen1-0/+2
When cdns_plat_pcie_probe() succeeds, return success instead of falling into the error handling code. Fixes: bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library") Link: https://lore.kernel.org/r/DM6PR19MB40271B93057D949310F0B0EDA0BF9@DM6PR19MB4027.namprd19.prod.outlook.com Signed-off-by: Xuliang Zhang <[email protected]> Signed-off-by: Li Chen <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Bjorn Helgaas <[email protected]> Cc: [email protected]
2021-11-03PCI: j721e: Fix j721e_pcie_probe() error pathChristophe JAILLET1-1/+1
If an error occurs after a successful cdns_pcie_init_phy() call, it must be undone by a cdns_pcie_disable_phy() call, as already done above and below. Update the goto to branch at the correct place of the error handling path. Link: https://lore.kernel.org/r/db477b0cb444891a17c4bb424467667dc30d0bab.1624794264.git.christophe.jaillet@wanadoo.fr Fixes: 49e0efdce791 ("PCI: j721e: Add support to provide refclk to PCIe connector") Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Krzysztof Wilczyński <[email protected]>
2021-09-02Merge branch 'remotes/lorenzo/pci/endpoint'Bjorn Helgaas2-53/+155
- Add max-virtual-functions to endpoint binding (Kishon Vijay Abraham I) - Add pci_epf_add_vepf() API to add virtual function to endpoint (Kishon Vijay Abraham I) - Add pci_epf_vepf_link() to link virtual function to endpoint physical function (Kishon Vijay Abraham I) - Add virtual function number to pci_epc_ops endpoint ops interfaces (Kishon Vijay Abraham I) - Simplify register base address computation for endpoint BAR configuration (Kishon Vijay Abraham I) - Add support to configure virtual functions in cadence endpoint driver (Kishon Vijay Abraham I) - Add SR-IOV configuration to endpoint test driver (Kishon Vijay Abraham I) - Document configfs usage to create virtual functions for endpoints (Kishon Vijay Abraham I) * remotes/lorenzo/pci/endpoint: Documentation: PCI: endpoint/pci-endpoint-cfs: Guide to use SR-IOV misc: pci_endpoint_test: Populate sriov_configure ops to configure SR-IOV device PCI: cadence: Add support to configure virtual functions PCI: cadence: Simplify code to get register base address for configuring BAR PCI: endpoint: Add virtual function number in pci_epc ops PCI: endpoint: Add support to link a physical function to a virtual function PCI: endpoint: Add support to add virtual function in endpoint core dt-bindings: PCI: pci-ep: Add binding to specify virtual function
2021-08-19PCI: j721e: Add PCIe support for AM64Kishon Vijay Abraham I1-0/+19
AM64 has the same PCIe IP as in J7200 with certain erratas not applicable (quirk_detect_quiet_flag). Add support for "ti,am64-pcie-host" compatible and "ti,am64-pcie-ep" compatible that is specific to AM64. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2021-08-19PCI: j721e: Add PCIe support for J7200Kishon Vijay Abraham I1-4/+36
J7200 has the same PCIe IP as in J721E with minor changes in the wrapper. J7200 allows byte access of bridge configuration space registers and the register field for LINK_DOWN interrupt is different. J7200 also requires "quirk_detect_quiet_flag" to be set. Configure these changes as part of driver data applicable only to J7200. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2021-08-19PCI: cadence: Add quirk flag to set minimum delay in LTSSM Detect.Quiet stateNadeem Athani4-0/+38
PCIe fails to link up if SERDES lanes not used by PCIe are assigned to another protocol. For example, link training fails if lanes 2 and 3 are assigned to another protocol while lanes 0 and 1 are used for PCIe to form a two lane link. This failure is due to an incorrect tie-off on an internal status signal indicating electrical idle. Status signals going from SERDES to PCIe Controller are tied-off when a lane is not assigned to PCIe. Signal indicating electrical idle is incorrectly tied-off to a state that indicates non-idle. As a result, PCIe sees unused lanes to be out of electrical idle and this causes LTSSM to exit Detect.Quiet state without waiting for 12ms timeout to occur. If a receiver is not detected on the first receiver detection attempt in Detect.Active state, LTSSM goes back to Detect.Quiet and again moves forward to Detect.Active state without waiting for 12ms as required by PCIe base specification. Since wait time in Detect.Quiet is skipped, multiple receiver detect operations are performed back-to-back without allowing time for capacitance on the transmit lines to discharge. This causes subsequent receiver detection to always fail even if a receiver gets connected eventually. Add a quirk flag "quirk_detect_quiet_flag" to program the minimum time the LTSSM should wait on entering Detect.Quiet state here. This has to be set for J7200 as it has an incorrect tie-off on unused lanes. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Nadeem Athani <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2021-08-19PCI: cadence: Use bitfield for *quirk_retrain_flag* instead of boolKishon Vijay Abraham I2-2/+2
No functional change. As we are intending to add additional 1-bit members in struct j721e_pcie_data/struct cdns_pcie_rc, use bitfields instead of bool since it takes less space. As discussed in [1], the preference is to use bitfileds instead of bool inside structures. [1] -> https://lore.kernel.org/linux-fsdevel/CA+55aFzKQ6Pj18TB8p4Yr0M4t+S+BsiHH=BJNmn=76-NcjTj-g@mail.gmail.com/ Suggested-by: Bjorn Helgaas <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2021-08-19PCI: cadence: Add support to configure virtual functionsKishon Vijay Abraham I2-21/+128
Now that support for SR-IOV is added in PCIe endpoint core, add support to configure virtual functions in the Cadence PCIe EP driver. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.