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No functional change. Simplify code to get register base address for
configuring PCI BAR.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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Add virtual function number in pci_epc ops. EPC controller driver
can perform virtual function specific initialization based on the
virtual function number.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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Fix kernel-doc formatting throughout drivers/pci and related include files.
No change to functionality intended.
Check for warnings:
$ find include drivers/pci -type f -path "*pci*.[ch]" | xargs scripts/kernel-doc -none
[bhelgaas: squashed to one commit]
Link: https://lore.kernel.org/r/[email protected]
Link: https://lore.kernel.org/r/[email protected]
Link: https://lore.kernel.org/r/[email protected]
Link: https://lore.kernel.org/r/[email protected]
Link: https://lore.kernel.org/r/[email protected]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Wilczyński <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull pci updates from Bjorn Helgaas:
"Enumeration:
- Release OF node when pci_scan_device() fails (Dmitry Baryshkov)
- Add pci_disable_parity() (Bjorn Helgaas)
- Disable Mellanox Tavor parity reporting (Heiner Kallweit)
- Disable N2100 r8169 parity reporting (Heiner Kallweit)
- Fix RCiEP device to RCEC association (Qiuxu Zhuo)
- Convert sysfs "config", "rom", "reset", "label", "index",
"acpi_index" to static attributes to help fix races in device
enumeration (Krzysztof Wilczyński)
- Convert sysfs "vpd" to static attribute (Heiner Kallweit, Krzysztof
Wilczyński)
- Use sysfs_emit() in "show" functions (Krzysztof Wilczyński)
- Remove unused alloc_pci_root_info() return value (Krzysztof
Wilczyński)
PCI device hotplug:
- Fix acpiphp reference count leak (Feilong Lin)
Power management:
- Fix acpi_pci_set_power_state() debug message (Rafael J. Wysocki)
- Fix runtime PM imbalance (Dinghao Liu)
Virtualization:
- Increase delay after FLR to work around Intel DC P4510 NVMe erratum
(Raphael Norwitz)
MSI:
- Convert rcar, tegra, xilinx to MSI domains (Marc Zyngier)
- For rcar, xilinx, use controller address as MSI doorbell (Marc
Zyngier)
- Remove unused hv msi_controller struct (Marc Zyngier)
- Remove unused PCI core msi_controller support (Marc Zyngier)
- Remove struct msi_controller altogether (Marc Zyngier)
- Remove unused default_teardown_msi_irqs() (Marc Zyngier)
- Let host bridges declare their reliance on MSI domains (Marc
Zyngier)
- Make pci_host_common_probe() declare its reliance on MSI domains
(Marc Zyngier)
- Advertise mediatek lack of built-in MSI handling (Thomas Gleixner)
- Document ways of ending up with NO_MSI (Marc Zyngier)
- Refactor HT advertising of NO_MSI flag (Marc Zyngier)
VPD:
- Remove obsolete Broadcom NIC VPD length-limiting quirk (Heiner
Kallweit)
- Remove sysfs VPD size checking dead code (Heiner Kallweit)
- Convert VPF sysfs file to static attribute (Heiner Kallweit)
- Remove unnecessary pci_set_vpd_size() (Heiner Kallweit)
- Tone down "missing VPD" message (Heiner Kallweit)
Endpoint framework:
- Fix NULL pointer dereference when epc_features not implemented
(Shradha Todi)
- Add missing destroy_workqueue() in endpoint test (Yang Yingliang)
Amazon Annapurna Labs PCIe controller driver:
- Fix compile testing without CONFIG_PCI_ECAM (Arnd Bergmann)
- Fix "no symbols" warnings when compile testing with
CONFIG_TRIM_UNUSED_KSYMS (Arnd Bergmann)
APM X-Gene PCIe controller driver:
- Fix cfg resource mapping regression (Dejin Zheng)
Broadcom iProc PCIe controller driver:
- Return zero for success of iproc_msi_irq_domain_alloc() (Pali
Rohár)
Broadcom STB PCIe controller driver:
- Add reset_control_rearm() stub for !CONFIG_RESET_CONTROLLER (Jim
Quinlan)
- Fix use of BCM7216 reset controller (Jim Quinlan)
- Use reset/rearm for Broadcom STB pulse reset instead of
deassert/assert (Jim Quinlan)
- Fix brcm_pcie_probe() error return for unsupported revision (Wei
Yongjun)
Cavium ThunderX PCIe controller driver:
- Fix compile testing (Arnd Bergmann)
- Fix "no symbols" warnings when compile testing with
CONFIG_TRIM_UNUSED_KSYMS (Arnd Bergmann)
Freescale Layerscape PCIe controller driver:
- Fix ls_pcie_ep_probe() syntax error (comma for semicolon)
(Krzysztof Wilczyński)
- Remove layerscape-gen4 dependencies on OF and ARM64, add dependency
on ARCH_LAYERSCAPE (Geert Uytterhoeven)
HiSilicon HIP PCIe controller driver:
- Remove obsolete HiSilicon PCIe DT description (Dongdong Liu)
Intel Gateway PCIe controller driver:
- Remove unused pcie_app_rd() (Jiapeng Chong)
Intel VMD host bridge driver:
- Program IRTE with Requester ID of VMD endpoint, not child device
(Jon Derrick)
- Disable VMD MSI-X remapping when possible so children can use more
MSI-X vectors (Jon Derrick)
MediaTek PCIe controller driver:
- Configure FC and FTS for functions other than 0 (Ryder Lee)
- Add YAML schema for MediaTek (Jianjun Wang)
- Export pci_pio_to_address() for module use (Jianjun Wang)
- Add MediaTek MT8192 PCIe controller driver (Jianjun Wang)
- Add MediaTek MT8192 INTx support (Jianjun Wang)
- Add MediaTek MT8192 MSI support (Jianjun Wang)
- Add MediaTek MT8192 system power management support (Jianjun Wang)
- Add missing MODULE_DEVICE_TABLE (Qiheng Lin)
Microchip PolarFlare PCIe controller driver:
- Make several symbols static (Wei Yongjun)
NVIDIA Tegra PCIe controller driver:
- Add MCFG quirks for Tegra194 ECAM errata (Vidya Sagar)
- Make several symbols const (Rikard Falkeborn)
- Fix Kconfig host/endpoint typo (Wesley Sheng)
SiFive FU740 PCIe controller driver:
- Add pcie_aux clock to prci driver (Greentime Hu)
- Use reset-simple in prci driver for PCIe (Greentime Hu)
- Add SiFive FU740 PCIe host controller driver and DT binding (Paul
Walmsley, Greentime Hu)
Synopsys DesignWare PCIe controller driver:
- Move MSI Receiver init to dw_pcie_host_init() so it is
re-initialized along with the RC in resume (Jisheng Zhang)
- Move iATU detection earlier to fix regression (Hou Zhiqiang)
TI J721E PCIe driver:
- Add DT binding and TI j721e support for refclk to PCIe connector
(Kishon Vijay Abraham I)
- Add host mode and endpoint mode DT bindings for TI AM64 SoC (Kishon
Vijay Abraham I)
TI Keystone PCIe controller driver:
- Use generic config accessors for TI AM65x (K3) to fix regression
(Kishon Vijay Abraham I)
Xilinx NWL PCIe controller driver:
- Add support for coherent PCIe DMA traffic using CCI (Bharat Kumar
Gogada)
- Add optional "dma-coherent" DT property (Bharat Kumar Gogada)
Miscellaneous:
- Fix kernel-doc warnings (Krzysztof Wilczyński)
- Remove unused MicroGate SyncLink device IDs (Jiri Slaby)
- Remove redundant dev_err() for devm_ioremap_resource() failure
(Chen Hui)
- Remove redundant initialization (Colin Ian King)
- Drop redundant dev_err() for platform_get_irq() errors (Krzysztof
Wilczyński)"
* tag 'pci-v5.13-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (98 commits)
riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC
PCI: fu740: Add SiFive FU740 PCIe host controller driver
dt-bindings: PCI: Add SiFive FU740 PCIe host controller
MAINTAINERS: Add maintainers for SiFive FU740 PCIe driver
clk: sifive: Use reset-simple in prci driver for PCIe driver
clk: sifive: Add pcie_aux clock in prci driver for PCIe driver
PCI: brcmstb: Use reset/rearm instead of deassert/assert
ata: ahci_brcm: Fix use of BCM7216 reset controller
reset: add missing empty function reset_control_rearm()
PCI: Allow VPD access for QLogic ISP2722
PCI/VPD: Add helper pci_get_func0_dev()
PCI/VPD: Remove pci_vpd_find_tag() SRDT handling
PCI/VPD: Remove pci_vpd_find_tag() 'offset' argument
PCI/VPD: Change pci_vpd_init() return type to void
PCI/VPD: Make missing VPD message less alarming
PCI/VPD: Remove pci_set_vpd_size()
x86/PCI: Remove unused alloc_pci_root_info() return value
MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer
PCI: mediatek-gen3: Add system PM support
PCI: mediatek-gen3: Add MSI support
...
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- Add DT binding and TI j721e support for refclk to PCIe connector (Kishon
Vijay Abraham I)
- Add host mode and endpoint mode DT bindings for TI AM64 SoC (Kishon Vijay
Abraham I)
* remotes/lorenzo/pci/cadence:
PCI: j721e: Add support to provide refclk to PCIe connector
dt-bindings: PCI: ti,j721e: Add endpoint mode dt-bindings for TI's AM64 SoC
dt-bindings: PCI: ti,j721e: Add host mode dt-bindings for TI's AM64 SoC
dt-bindings: PCI: ti,j721e: Add binding to represent refclk to the connector
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list_sort() internally casts the comparison function passed to it
to a different type with constant struct list_head pointers, and
uses this pointer to call the functions, which trips indirect call
Control-Flow Integrity (CFI) checking.
Instead of removing the consts, this change defines the
list_cmp_func_t type and changes the comparison function types of
all list_sort() callers to use const pointers, thus avoiding type
mismatches.
Suggested-by: Nick Desaulniers <[email protected]>
Signed-off-by: Sami Tolvanen <[email protected]>
Reviewed-by: Nick Desaulniers <[email protected]>
Reviewed-by: Christoph Hellwig <[email protected]>
Reviewed-by: Kees Cook <[email protected]>
Tested-by: Nick Desaulniers <[email protected]>
Tested-by: Nathan Chancellor <[email protected]>
Signed-off-by: Kees Cook <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Add support to provide refclk to PCIe connector.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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Fix kernel-doc formatting errors, function names that don't match the doc,
and some missing parameter documentation. These are reported by:
make W=1 drivers/pci/
No functional change intended.
[bhelgaas: squashed into one patch since this only changes comments]
Link: https://lore.kernel.org/r/[email protected]
Link: https://lore.kernel.org/r/[email protected]
Link: https://lore.kernel.org/r/[email protected]
Link: https://lore.kernel.org/r/[email protected]
Link: https://lore.kernel.org/r/[email protected]
Link: https://lore.kernel.org/r/[email protected]
Link: https://lore.kernel.org/r/[email protected]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Wilczyński <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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- Account for 64-bit BARs in pci_epc_get_first_free_bar() (Kishon Vijay
Abraham I)
- Add pci_epc_get_next_free_bar() helper (Kishon Vijay Abraham I)
- Return error codes on failure of endpoint BAR interfaces (Kishon Vijay
Abraham I)
- Remove unused pci_epf_match_device() (Kishon Vijay Abraham I)
- Add support for secondary endpoint controller to prepare for NTB endpoint
functionality (Kishon Vijay Abraham I)
- Add configfs support for secondary endpoint controller (Kishon Vijay
Abraham I)
- Add MSI address mapping ops for NTB doorbell support (Kishon Vijay
Abraham I)
- Add ops for endpoint function-specific attributes (Kishon Vijay Abraham
I)
- Allow configfs subdirectory for endpoint function configuration (Kishon
Vijay Abraham I)
- Implement cadence MSI address mapping ops (Kishon Vijay Abraham I)
- Configure cadence LM_EP_FUNC_CFG based on epc->function_num_map (Kishon
Vijay Abraham I)
- Add endpoint-side driver to provide NTB functionality (Kishon Vijay
Abraham I)
- Add host-side driver for generic EPF NTB functionality (Kishon Vijay
Abraham I)
- Document NTB endpoint functionality (Kishon Vijay Abraham I)
* pci/ntb:
Documentation: PCI: Add PCI endpoint NTB function user guide
Documentation: PCI: Add configfs binding documentation for pci-ntb endpoint function
NTB: Add support for EPF PCI Non-Transparent Bridge
PCI: Add TI J721E device to PCI IDs
PCI: endpoint: Add EP function driver to provide NTB functionality
PCI: cadence: Configure LM_EP_FUNC_CFG based on epc->function_num_map
PCI: cadence: Implement ->msi_map_irq() ops
PCI: endpoint: Allow user to create sub-directory of 'EPF Device' directory
PCI: endpoint: Add pci_epf_ops to expose function-specific attrs
PCI: endpoint: Add pci_epc_ops to map MSI IRQ
PCI: endpoint: Add support in configfs to associate two EPCs with EPF
PCI: endpoint: Add support to associate secondary EPC with EPF
PCI: endpoint: Remove unused pci_epf_match_device()
PCI: endpoint: Make *_free_bar() to return error codes on failure
PCI: endpoint: Add helper API to get the 'next' unreserved BAR
PCI: endpoint: Make *_get_first_free_bar() take into account 64 bit BAR
Documentation: PCI: Add specification for the PCI NTB function device
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- Retrain Link to work around Gen2 training defect (Nadeem Athani)
* remotes/lorenzo/pci/cadence:
PCI: cadence: Retrain Link to work around Gen2 training defect
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The number of functions supported by the endpoint controller is configured
in LM_EP_FUNC_CFG based on func_no member of struct pci_epf. Now that an
endpoint function can be associated with two endpoint controllers (primary
and secondary), just using func_no will not suffice as that will take into
account only if the endpoint controller is associated with the primary
interface of endpoint function. Instead use epc->function_num_map which
will already have the configured functions information (irrespective of
whether the endpoint controller is associated with primary or secondary
interface).
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Tom Joseph <[email protected]>
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Implement ->msi_map_irq() ops in order to map physical address to MSI
address and return MSI data.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Tom Joseph <[email protected]>
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Function cdns_pcie_host_map_dma_ranges() iterates over a PCIe host bridge
DMA ranges using the resource_list_for_each_entry() iterator, returning an
error if cdns_pcie_host_bar_config() fails.
49e427e6bdd1 ("Merge branch 'pci/host-probe-refactor'") botched a merge so
it *always* returned after the first DMA range, even if no error occurred.
Fix the error checking so we return early only when an error occurs.
[bhelgaas: commit log]
Fixes: 49e427e6bdd1 ("Merge branch 'pci/host-probe-refactor'")
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Wilczyński <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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Cadence controller will not initiate autonomous speed change if strapped
as Gen2. The Retrain Link bit is set as quirk to enable this speed change.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Nadeem Athani <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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Get "syscon" pcie_ctrl offset from the argument of "ti,syscon-pcie-ctrl"
phandle. Previously a subnode to "syscon" node was added which has the
exact memory mapped address of pcie_ctrl but now the offset of pcie_ctrl
within "syscon" is now being passed as argument to "ti,syscon-pcie-ctrl"
phandle.
If the offset is not provided in "ti,syscon-pcie-ctrl", the
full memory mapped address of pcie_ctrl is used in order to maintain old
DT compatibility.
This change is as discussed in [1]
[1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
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Now that "cdns,max-outbound-regions" is made an optional property, do
not error out if "cdns,max-outbound-regions" device tree property is
not found.
Link: http://lore.kernel.org/r/20201105165331.GA55814@bogus
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
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expression
Simplify the return expression.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Qinglang Miao <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
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This comment still refers to the old driver pathname,
when all PCI drivers were located directly under the
drivers/pci directory.
Anyway the function name itself is enough, so we can
remove the overabundant path reference.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Flavio Suligoi <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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- Use pci_host_bridge.windows list directly instead of splicing in a
temporary list for cadence, mvebu, host-common (Rob Herring)
- Use pci_host_probe() instead of open-coding all the pieces for altera,
brcmstb, iproc, mobiveil, rcar, rockchip, tegra, v3, versatile, xgene,
xilinx, xilinx-nwl (Rob Herring)
- Convert to devm_platform_ioremap_resource_byname() instead of open-coding
platform_get_resource_byname() and devm_ioremap_resource() for altera,
cadence, mediatek, rockchip, tegra, xgene (Dejin Zheng)
- Convert to devm_platform_ioremap_resource() instead of open-coding
platform_get_resource() and devm_ioremap_resource() for aardvark,
brcmstb, exynos, ftpci100, versatile (Dejin Zheng)
- Remove redundant error messages from devm_pci_remap_cfg_resource()
callers (Dejin Zheng)
- Drop useless PCI_ENABLE_PROC_DOMAINS from versatile driver (Rob Herring)
- Default host bridge parent device to the platform device (Rob Herring)
- Drop unnecessary zeroing of host bridge fields (Rob Herring)
- Use pci_is_root_bus() instead of tracking root bus number separately in
aardvark, designware (imx6, keystone, designware-host), mobiveil,
xilinx-nwl, xilinx, rockchip, rcar (Rob Herring)
- Set host bridge bus number in pci_scan_root_bus_bridge() instead of each
driver for aardvark, designware-host, host-common, mediatek, rcar, tegra,
v3-semi (Rob Herring)
- Use bridge resources instead of parsing DT 'ranges' again for cadence
(Rob Herring)
- Remove private bus number and range from cadence (Rob Herring)
- Use devm_pci_alloc_host_bridge() to simplify rcar (Rob Herring)
- Use struct pci_host_bridge.windows list directly rather than a temporary
(Rob Herring)
- Reduce OF "missing non-prefetchable window" from error to warning message
(Rob Herring)
- Convert rcar-gen2 from old Arm-specific pci_common_init_dev() to new
arch-independent interfaces (Rob Herring)
- Move DT resource setup into devm_pci_alloc_host_bridge() (Rob Herring)
- Set bridge map_irq and swizzle_irq to default functions; drivers that
don't support legacy IRQs (iproc) need to undo this (Rob Herring)
* pci/host-probe-refactor:
PCI: Set bridge map_irq and swizzle_irq to default functions
PCI: Move DT resource setup into devm_pci_alloc_host_bridge()
PCI: rcar-gen2: Convert to use modern host bridge probe functions
PCI: of: Reduce missing non-prefetchable memory region to a warning
PCI: rcar: Use struct pci_host_bridge.windows list directly
PCI: rcar: Use devm_pci_alloc_host_bridge()
PCI: cadence: Remove private bus number and range storage
PCI: cadence: Use bridge resources for outbound window setup
PCI: Move setting pci_host_bridge.busnr out of host drivers
PCI: rcar: Use pci_is_root_bus() to check if bus is root bus
PCI: rockchip: Use pci_is_root_bus() to check if bus is root bus
PCI: xilinx: Use pci_is_root_bus() to check if bus is root bus
PCI: xilinx-nwl: Use pci_is_root_bus() to check if bus is root bus
PCI: mobiveil: Use pci_is_root_bus() to check if bus is root bus
PCI: designware: Use pci_is_root_bus() to check if bus is root bus
PCI: aardvark: Use pci_is_root_bus() to check if bus is root bus
PCI: Drop unnecessary zeroing of bridge fields
PCI: Set default bridge parent device
PCI: versatile: Drop flag PCI_ENABLE_PROC_DOMAINS
PCI: controller: Remove duplicate error message
PCI: controller: Convert to devm_platform_ioremap_resource()
PCI: controller: Convert to devm_platform_ioremap_resource_byname()
PCI: xilinx: Use pci_host_probe() to register host
PCI: xilinx-nwl: Use pci_host_probe() to register host
PCI: rockchip: Use pci_host_probe() to register host
PCI: rcar: Use pci_host_probe() to register host
PCI: iproc: Use pci_host_probe() to register host
PCI: altera: Use pci_host_probe() to register host
PCI: xgene: Use pci_host_probe() to register host
PCI: versatile: Use pci_host_probe() to register host
PCI: v3: Use pci_host_probe() to register host
PCI: tegra: Use pci_host_probe() to register host
PCI: mobiveil: Use pci_host_probe() to register host
PCI: brcmstb: Use pci_host_probe() to register host
PCI: host-common: Use struct pci_host_bridge.windows list directly
PCI: mvebu: Use struct pci_host_bridge.windows list directly
PCI: cadence: Use struct pci_host_bridge.windows list directly
# Conflicts:
# drivers/pci/controller/cadence/pcie-cadence-host.c
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- Fix runtime power management imbalance for cadence, dra7xx, qcom, rcar
(Dinghao Liu)
* remotes/lorenzo/pci/runtime-pm:
PCI: rcar: Fix runtime PM imbalance on error
PCI: qcom: Fix runtime PM imbalance on error
PCI: cadence: Fix runtime PM imbalance on error
PCI: dwc: pci-dra7xx: Fix runtime PM imbalance on error
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The majority of DT based host drivers use the default .map_irq() and
.swizzle_irq() functions, so let's initialize the function pointers to
the default and drop setting them in the host drivers.
Drivers like iProc which don't support legacy interrupts need to set
.map_irq() back to NULL.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Bjorn Helgaas <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
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Now that pci_parse_request_of_pci_ranges() callers just setup
pci_host_bridge.windows and dma_ranges directly and don't need the bus
range returned, we can just initialize them when allocating the
pci_host_bridge struct.
With this, pci_parse_request_of_pci_ranges() becomes a static function.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Bjorn Helgaas <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
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Add support for PCIe controller in J721E SoC. The controller uses the
Cadence PCIe core programmed by pcie-cadence*.c. The PCIe controller
will work in both host mode and device mode.
Some of the features of the controller are:
*) Supports both RC mode and EP mode
*) Supports MSI and MSI-X support
*) Supports upto GEN3 speed mode
*) Supports SR-IOV capability
*) Ability to route all transactions via SMMU (support will be added
in a later patch).
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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Implement ->set_msix() and ->get_msix() callback functions in order
to configure MSIX capability in the PCIe endpoint controller.
Add cdns_pcie_ep_send_msix_irq() to send MSIX interrupts to Host.
cdns_pcie_ep_send_msix_irq() gets the MSIX table address (virtual
address) from "struct cdns_pcie_epf" that gets initialized in
->set_bar() call back function.
[[email protected]: Re-implement MSIX support in accordance with the
re-designed core MSI-X interfaces]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alan Douglas <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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Commit 1b79c5284439 ("PCI: cadence: Add host driver for Cadence PCIe
controller") in order to update Vendor ID, directly wrote to
PCI_VENDOR_ID register. However PCI_VENDOR_ID in root port configuration
space is read-only register and writing to it will have no effect.
Use local management register to configure Vendor ID and Subsystem Vendor
ID.
Link: https://lore.kernel.org/r/[email protected]
Fixes: 1b79c5284439 ("PCI: cadence: Add host driver for Cadence PCIe controller")
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
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Cadence driver uses "mem" memory resource to obtain the offset of
configuration space address region, memory space address region and
message space address region. The obtained offset is used to program
the Address Translation Unit (ATU). However certain platforms like TI's
J721E SoC require the absolute address to be programmed in the ATU and
not just the offset. Add new *ops* for CPU addr fixup for the platform
drivers to provide the correct address to be programmed in the ATU.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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Certain platforms like TI's J721E allows only 32-bit configuration
space access. In such cases pci_generic_config_read and
pci_generic_config_write cannot be used. Add support in Cadence core
to let pci_host_bridge have custom pci_ops.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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Add cdns_pcie_ops to start link and verify link status. The registers
to start link and to check link status is in Platform specific PCIe
wrapper. Add support for platform specific drivers to add callback
functions for the PCIe Cadence core to start link and verify link status.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
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Certain platforms like TI's J721E using Cadence PCIe IP can perform only
32-bit accesses for reading or writing to Cadence registers. Convert all
read and write accesses to 32-bit in Cadence PCIe driver in preparation
for adding PCIe support in TI's J721E SoC.
Also add spin lock to disable interrupts while modifying PCI_STATUS
register while raising legacy interrupt since PCI_STATUS is accessible
by both remote RC and EP and time between read and write should be
minimized.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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commit bd22885aa188 ("PCI: cadence: Refactor driver to use as a core
library") while refactoring the Cadence PCIe driver to be used as
library, removed pm_runtime_get_sync() from cdns_pcie_ep_setup()
and cdns_pcie_host_setup() but missed to remove the corresponding
pm_runtime_put_sync() in the error path. Fix it here.
Link: https://lore.kernel.org/r/[email protected]
Fixes: bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library")
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
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Cadence PCIe core driver (host mode) uses "cdns,no-bar-match-nbits"
property to configure the number of bits passed through from PCIe
address to internal address in Inbound Address Translation register.
This only used the NO MATCH BAR.
However standard PCI dt-binding already defines "dma-ranges" to
describe the address ranges accessible by PCIe controller. Add support
in Cadence PCIe host driver to parse dma-ranges and configure the
inbound regions for BAR0, BAR1 and NO MATCH BAR. Cadence IP specifies
maximum size for BAR0 as 256GB, maximum size for BAR1 as 2 GB.
This adds support to take the next biggest region in "dma-ranges" and
find the smallest BAR that each of the regions fit in and if there is
no BAR big enough to hold the region, split the region to see if it can
be fitted using multiple BARs.
"dma-ranges" of J721E will be
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
Since there is no BAR which can hold 2^48 size, NO_MATCH_BAR will be
used here.
Legacy device tree binding compatibility is maintained by retaining
support for "cdns,no-bar-match-nbits".
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
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There's no need to store the bus number or range resource as the driver
only needs the bus number which is already in the pci_host_bridge.
For endpoint mode, the bus number is always 0.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Bjorn Helgaas <[email protected]>
Cc: Tom Joseph <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
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Instead of parsing 'ranges' from DT again, use the bridge window
resources.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Bjorn Helgaas <[email protected]>
Cc: Tom Joseph <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
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The host bridge's parent device is always the platform device. As we
already have a pointer to it in the devres functions, let's initialize
the parent device. Drivers can still override the parent if desired.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Bjorn Helgaas <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
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devm_pci_remap_cfg_resource() will print an error message by itself when
goes wrong, so remove the duplicate error message.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Dejin Zheng <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
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Use devm_platform_ioremap_resource_byname() to simplify the code,
since it calls respectively platform_get_resource_byname() and
devm_ioremap_resource().
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Dejin Zheng <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Gustavo Pimentel <[email protected]>
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pm_runtime_get_sync() increments the runtime PM usage counter even
it returns an error code. Thus a pairing decrement is needed on
the error handling path to keep the counter balanced.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Dinghao Liu <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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There's no need to create a temporary resource list and then splice it to
struct pci_host_bridge.windows list. Just use pci_host_bridge.windows
directly. The necessary clean-up is already handled by the PCI core.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: Tom Joseph <[email protected]>
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- Fix rcar OB window programming (Andrew Murray)
- Add rcar suspend/resume support (Kazufumi Ikeda)
- Add r8a77961 to DT binding (Yoshihiro Shimoda)
- Rename pcie-rcar.c to pcie-rcar-host.c to make room for endpoint mode
(Lad Prabhakar)
- Move shareable code to pcie-rcar.c (Lad Prabhakar)
- Correct PCIEPAMR mask calculation for "size < 128" (Lad Prabhakar)
- Add endpoint support for multiple outbound memory windows (Lad
Prabhakar)
- Add R-Car PCIe endpoint driver and DT bindings (Lad Prabhakar)
* remotes/lorenzo/pci/rcar:
MAINTAINERS: Add file patterns for rcar PCI device tree bindings
PCI: rcar: Add endpoint mode support
dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller
PCI: endpoint: Add support to handle multiple base for mapping outbound memory
PCI: endpoint: Pass page size as argument to pci_epc_mem_init()
PCI: rcar: Fix calculating mask for PCIEPAMR register
PCI: rcar: Move shareable code to a common file
PCI: rcar: Rename pcie-rcar.c to pcie-rcar-host.c
dt-bindings: pci: rcar: add r8a77961 support
PCI: rcar: Add suspend/resume
PCI: rcar: Fix incorrect programming of OB windows
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The PCI Bus Binding specification (IEEE Std 1275-1994 Revision 2.1 [1])
defines both Vendor ID and Device ID to be 32-bits. Fix
pcie-cadence-host.c driver to read 32-bit Vendor ID and Device ID
properties from device tree.
[1] -> https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Rob Herring <[email protected]>
Acked-by: Tom Joseph <[email protected]>
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"cdns,max-outbound-regions" device tree property provides the
maximum number of outbound regions supported by the Host PCIe
controller. However the outbound regions are configured based
on what is populated in the "ranges" DT property.
Avoid using two properties for configuring outbound regions and
use only "ranges" property instead.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Rob Herring <[email protected]>
Acked-by: Tom Joseph <[email protected]>
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pci_epc_mem_init() internally used page size equal to *PAGE_SIZE* to
manage the address space so instead just pass the page size as a
argument to pci_epc_mem_init().
Also make pci_epc_mem_init() as a C function instead of a macro function
in preparation for adding support for pci-epc-mem core to handle multiple
windows.
Link: https://lore.kernel.org/r/1588854799-13710-5-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Lad Prabhakar <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Yoshihiro Shimoda <[email protected]>
Acked-by: Kishon Vijay Abraham I <[email protected]>
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- Consolidate DT "dma-ranges" parsing and convert all host drivers to use
shared parsing (Rob Herring)
* remotes/lorenzo/pci/mmio-dma-ranges:
PCI: Make devm_of_pci_get_host_bridge_resources() static
PCI: rcar: Use inbound resources for setup
PCI: iproc: Use inbound resources for setup
PCI: xgene: Use inbound resources for setup
PCI: v3-semi: Use inbound resources for setup
PCI: ftpci100: Use inbound resources for setup
PCI: of: Add inbound resource parsing to helpers
PCI: versatile: Enable COMPILE_TEST
PCI: versatile: Remove usage of PHYS_OFFSET
PCI: versatile: Use pci_parse_request_of_pci_ranges()
PCI: xilinx-nwl: Use pci_parse_request_of_pci_ranges()
PCI: xilinx: Use pci_parse_request_of_pci_ranges()
PCI: xgene: Use pci_parse_request_of_pci_ranges()
PCI: v3-semi: Use pci_parse_request_of_pci_ranges()
PCI: rockchip: Drop storing driver private outbound resource data
PCI: rockchip: Use pci_parse_request_of_pci_ranges()
PCI: mobiveil: Use pci_parse_request_of_pci_ranges()
PCI: mediatek: Use pci_parse_request_of_pci_ranges()
PCI: iproc: Use pci_parse_request_of_pci_ranges()
PCI: faraday: Use pci_parse_request_of_pci_ranges()
PCI: dwc: Use pci_parse_request_of_pci_ranges()
PCI: altera: Use pci_parse_request_of_pci_ranges()
PCI: aardvark: Use pci_parse_request_of_pci_ranges()
PCI: Export pci_parse_request_of_pci_ranges()
resource: Add a resource_list_first_type helper
# Conflicts:
# drivers/pci/controller/pcie-rcar.c
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- Refactor Cadence PCIe host controller to use as a library for both host
and endpoint (Tom Joseph)
* remotes/lorenzo/pci/cadence:
PCI: cadence: Move all files to per-device cadence directory
PCI: cadence: Refactor driver to use as a core library
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Cadence core library files may be used by various platform drivers.
Add a new directory "cadence" to group all the Cadence core library files
and the platforms using Cadence core library.
Signed-off-by: Tom Joseph <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
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