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2024-07-14net: phy: bcm54811: New link mode for BroadR-ReachKamil Horák (2N)1-1/+2
Introduce a new link mode necessary for 10 MBit single-pair connection in BroadR-Reach mode on bcm5481x PHY by Broadcom. This new link mode, 10baseT1BRR, is known as 1BR10 in the Broadcom terminology. Another link mode to be used is 1BR100 and it is already present as 100baseT1, because Broadcom's 1BR100 became 100baseT1 (IEEE 802.3bw). Signed-off-by: Kamil Horák (2N) <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-06-18net: phy: introduce core support for phy-mode = "10g-qxgmii"Vladimir Oltean1-0/+1
10G-QXGMII is a MAC-to-PHY interface defined by the USXGMII multiport specification. It uses the same signaling as USXGMII, but it multiplexes 4 ports over the link, resulting in a maximum speed of 2.5G per port. Some in-tree SoCs like the NXP LS1028A use "usxgmii" when they mean either the single-port USXGMII or the quad-port 10G-QXGMII variant, and they could get away just fine with that thus far. But there is a need to distinguish between the 2 as far as SerDes drivers are concerned. Signed-off-by: Vladimir Oltean <[email protected]> Signed-off-by: Luo Jie <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Reviewed-by: Russell King (Oracle) <[email protected]> Signed-off-by: Paolo Abeni <[email protected]>
2023-12-17net: phy: add support for PHY package MMD read/writeChristian Marangi1-0/+140
Some PHY in PHY package may require to read/write MMD regs to correctly configure the PHY package. Add support for these additional required function in both lock and no lock variant. It's assumed that the entire PHY package is either C22 or C45. We use C22 or C45 way of writing/reading to mmd regs based on the passed phydev whether it's C22 or C45. Signed-off-by: Christian Marangi <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-12-17net: phy: restructure __phy_write/read_mmd to helper and phydev userChristian Marangi1-34/+30
Restructure phy_write_mmd and phy_read_mmd to implement generic helper for direct mdiobus access for mmd and use these helper for phydev user. This is needed in preparation of PHY package API that requires generic access to the mdiobus and are deatched from phydev struct but instead access them based on PHY package base_addr and offsets. Signed-off-by: Christian Marangi <[email protected]> Reviewed-by: Russell King (Oracle) <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-08-14net: phy: Introduce PSGMII PHY interface modeGabor Juhos1-0/+2
The PSGMII interface is similar to QSGMII. The main difference is that the PSGMII interface combines five SGMII lines into a single link while in QSGMII only four lines are combined. Similarly to the QSGMII, this interface mode might also needs special handling within the MAC driver. It is commonly used by Qualcomm with their QCA807x PHY series and modern WiSoC-s. Add definitions for the PHY layer to allow to express this type of connection between the MAC and PHY. Signed-off-by: Gabor Juhos <[email protected]> Signed-off-by: Robert Marko <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-01-11drivers/net/phy: add the link modes for the 10BASE-T1S Ethernet PHYPiergiorgio Beruto1-1/+4
This patch adds the link modes for the IEEE 802.3cg Clause 147 10BASE-T1S Ethernet PHY. According to the specifications, the 10BASE-T1S supports Point-To-Point Full-Duplex, Point-To-Point Half-Duplex and/or Point-To-Multipoint (AKA Multi-Drop) Half-Duplex operations. Signed-off-by: Piergiorgio Beruto <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-10-24ethtool: Add support for 800Gbps link modesAmit Cohen1-1/+10
Add support for 800Gbps speed, link modes of 100Gbps per lane. As mentioned in slide 21 in IEEE documentation [1], all adopted 802.3df copper and optical PMDs baselines using 100G/lane will be supported. Add the relevant PMDs which are mentioned in slide 5 in IEEE documentation [1] and were approved on 10-2022 [2]: BP - KR8 Cu Cable - CR8 MMF 50m - VR8 MMF 100m - SR8 SMF 500m - DR8 SMF 2km - DR8-2 [1]: https://www.ieee802.org/3/df/public/22_10/22_1004/shrikhande_3df_01a_221004.pdf [2]: https://ieee802.org/3/df/KeyMotions_3df_221005.pdf Signed-off-by: Amit Cohen <[email protected]> Reviewed-by: Ido Schimmel <[email protected]> Signed-off-by: Petr Machata <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-09-23net: phy: Add support for rate matchingSean Anderson1-0/+21
This adds support for rate matching (also known as rate adaptation) to the phy subsystem. The general idea is that the phy interface runs at one speed, and the MAC throttles the rate at which it sends packets to the link speed. There's a good overview of several techniques for achieving this at [1]. This patch adds support for three: pause-frame based (such as in Aquantia phys), CRS-based (such as in 10PASS-TS and 2BASE-TL), and open-loop-based (such as in 10GBASE-W). This patch makes a few assumptions and a few non assumptions about the types of rate matching available. First, it assumes that different phys may use different forms of rate matching. Second, it assumes that phys can use rate matching for any of their supported link speeds (e.g. if a phy supports 10BASE-T and XGMII, then it can adapt XGMII to 10BASE-T). Third, it does not assume that all interface modes will use the same form of rate matching. Fourth, it does not assume that all phy devices will support rate matching (even if some do). Relaxing or strengthening these (non-)assumptions could result in a different API. For example, if all interface modes were assumed to use the same form of rate matching, then a bitmask of interface modes supportting rate matching would suffice. For some better visibility into the process, the current rate matching mode is exposed as part of the ethtool ksettings. For the moment, only read access is supported. I'm not sure what userspace might want to configure yet (disable it altogether, disable just one mode, specify the mode to use, etc.). For the moment, since only pause-based rate adaptation support is added in the next few commits, rate matching can be disabled altogether by adjusting the advertisement. 802.3 calls this feature "rate adaptation" in clause 49 (10GBASE-R) and "rate matching" in clause 61 (10PASS-TL and 2BASE-TS). Aquantia also calls this feature "rate adaptation". I chose "rate matching" because it is shorter, and because Russell doesn't think "adaptation" is correct in this context. Signed-off-by: Sean Anderson <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-09-05net: phy: Add 1000BASE-KX interface modeSean Anderson1-0/+1
Add 1000BASE-KX interface mode. This 1G backplane ethernet as described in clause 70. Clause 73 autonegotiation is mandatory, and only full duplex operation is supported. Although at the PMA level this interface mode is identical to 1000BASE-X, it uses a different form of in-band autonegation. This justifies a separate interface mode, since the interface mode (along with the MLO_AN_* autonegotiation mode) sets the type of autonegotiation which will be used on a link. This results in more than just electrical differences between the link modes. With regard to 1000BASE-X, 1000BASE-KX holds a similar position to SGMII: same signaling, but different autonegotiation. PCS drivers (which typically handle in-band autonegotiation) may only support 1000BASE-X, and not 1000BASE-KX. Similarly, the phy mode is used to configure serdes phys with phy_set_mode_ext. Due to the different electrical standards (SFI or XFI vs Clause 70), they will likely want to use different configuration. Adding a phy interface mode for 1000BASE-KX helps simplify configuration in these areas. Signed-off-by: Sean Anderson <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-08-22net: phy: Add helper to derive the number of ports from a phy modeMaxime Chevallier1-0/+52
Some phy modes such as QSGMII multiplex several MAC<->PHY links on one single physical interface. QSGMII used to be the only one supported, but other modes such as QUSGMII also carry multiple links. This helper allows getting the number of links that are multiplexed on a given interface. Signed-off-by: Maxime Chevallier <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-05-01ethtool: Add 10base-T1L link mode entryAlexandru Tachici1-1/+2
Add entry for the 10base-T1L full duplex mode. Reviewed-by: Andrew Lunn <[email protected]> Reviewed-by: Oleksij Rempel <[email protected]> Signed-off-by: Alexandru Tachici <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-01-31phy: make phy_set_max_speed() *void*Sergey Shtylyov1-14/+8
After following the call tree of phy_set_max_speed(), it became clear that this function never returns anything but 0, so we can change its result type to *void* and drop the result checks from the three drivers that actually bothered to do it... Found by Linux Verification Center (linuxtesting.org) with the SVACE static analysis tool. Signed-off-by: Sergey Shtylyov <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-12-09net: phy: prefer 1000baseT over 1000baseKXRussell King (Oracle)1-1/+1
The PHY settings table is supposed to be sorted by descending match priority - in other words, earlier entries are preferred over later entries. The order of 1000baseKX/Full and 1000baseT/Full is such that we prefer 1000baseKX/Full over 1000baseT/Full, but 1000baseKX/Full is a lot rarer than 1000baseT/Full, and thus is much less likely to be preferred. This causes phylink problems - it means a fixed link specifying a speed of 1G and full duplex gets an ethtool linkmode of 1000baseKX/Full rather than 1000baseT/Full as would be expected - and since we offer userspace a software emulation of a conventional copper PHY, we want to offer copper modes in preference to anything else. However, we do still want to allow the rarer modes as well. Hence, let's reorder these two modes to prefer copper. Tested-by: Tom Lendacky <[email protected]> Signed-off-by: Russell King (Oracle) <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Reported-by: Florian Fainelli <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2021-06-16net: phy: correct format of block commentsWenpeng Liang1-1/+2
Block comments should not use a trailing */ on a separate line and every line of a block comment should start with an '*'. Signed-off-by: Wenpeng Liang <[email protected]> Signed-off-by: Weihang Li <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2020-09-23net: phy: Document core PHY structuresAndrew Lunn1-1/+31
Add kerneldoc for the core PHY data structures, a few inline functions and exported functions which are not already documented. v2 Typos g/phy/PHY/s Signed-off-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2020-09-19ethtool: Add 100base-FX link mode entriesDan Murphy1-1/+3
Add entries for the 100base-FX full and half duplex supported modes. $ ethtool eth0 Supported ports: [ FIBRE ] Supported link modes: 100baseFX/Half 100baseFX/Full Supported pause frame use: Symmetric Receive-only Supports auto-negotiation: No Supported FEC modes: Not reported Advertised link modes: 100baseFX/Half 100baseFX/Full Advertised pause frame use: No Advertised auto-negotiation: No Advertised FEC modes: Not reported Speed: 100Mb/s Duplex: Full Auto-negotiation: off Port: MII PHYAD: 1 Transceiver: external Supports Wake-on: gs Wake-on: d SecureOn password: 00:00:00:00:00:00 Current message level: 0x00000000 (0) Link detected: yes Signed-off-by: Dan Murphy <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2020-07-08ethtool: Add support for 100Gbps per lane link modesMeir Lichtinger1-1/+16
Define 100G, 200G and 400G link modes using 100Gbps per lane LR, ER and FR are defined as a single link mode because they are using same technology and by design are fully interoperable. EEPROM content indicates if the module is LR, ER, or FR, and the user space ethtool decoder is planned to support decoding these modes in the EEPROM. Signed-off-by: Meir Lichtinger <[email protected]> CC: Andrew Lunn <[email protected]> Reviewed-by: Aya Levin <[email protected]> Signed-off-by: Saeed Mahameed <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2020-05-26net: mdiobus: add clause 45 mdiobus accessorsRussell King1-7/+4
There is a recurring pattern throughout some of the PHY code converting a devad and regnum to our packed clause 45 representation. Rather than having this scattered around the code, let's put a common translation function in mdio.h, and provide some register accessors. Convert the phylib core, phylink, bcm87xx and cortina to use these. Signed-off-by: Russell King <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2020-03-23net: phy: add and use phy_check_downshiftHeiner Kallweit1-0/+38
So far PHY drivers have to check whether a downshift occurred to be able to notify the user. To make life of drivers authors a little bit easier move the downshift notification to phylib. phy_check_downshift() compares the highest mutually advertised speed with the actual value of phydev->speed (typically read by the PHY driver from a vendor-specific register) to detect a downshift. v2: - Add downshift hint to phy_print_status Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2020-03-17net: mdiobus: add APIs for modifying a MDIO device registerRussell King1-31/+0
Add APIs for modifying a MDIO device register, similar to the existing phy_modify() group of functions, but at mdiobus level instead. Adapt __phy_modify_changed() to use the new mdiobus level helper. Signed-off-by: Russell King <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2020-02-18ethtool: Add support for low latency RS FECAya Levin1-1/+1
Add support for low latency Reed Solomon FEC as LLRS. The LL-FEC is defined by the 25G/50G ethernet consortium, in the document titled "Low Latency Reed Solomon Forward Error Correction" Signed-off-by: Aya Levin <[email protected]> Reviewed-by: Eran Ben Elisha <[email protected]> CC: Andrew Lunn <[email protected]> Signed-off-by: Saeed Mahameed <[email protected]> Reviewed-by: Andrew Lunn <[email protected]>
2020-01-20net: phy: don't crash in phy_read/_write_mmd without a PHY driverAlex Marginean1-2/+2
The APIs can be used by Ethernet drivers without actually loading a PHY driver. This may become more widespread in the future with 802.3z compatible MAC PCS devices being locally driven by the MAC driver when configuring for a PHY mode with in-band negotiation. Check that drv is not NULL before reading from it. Signed-off-by: Alex Marginean <[email protected]> Signed-off-by: Vladimir Oltean <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-11-25net: phy: add helpers phy_(un)lock_mdio_busHeiner Kallweit1-14/+14
Add helpers to make locking/unlocking the MDIO bus easier. Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-10-18net: phy: avoid NPE if read_page/write_page callbacks are not availableHeiner Kallweit1-0/+6
Currently there's a bug in the module subsystem [0] preventing load of the PHY driver module on certain systems (as one symptom). This results in a NPE on such systems for the following reason: Instead of the correct PHY driver the genphy driver is loaded that doesn't implement the read_page/write_page callbacks. Every call to phy_read_paged() et al will result in a NPE therefore. In parallel to fixing the root cause we should make sure that this one and maybe similar issues in other subsystems don't result in a NPE in phylib. So let's check for the callbacks before using them and warn once if they are not available. [0] https://marc.info/?t=157072642100001&r=1&w=2 Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-10-15ethtool: Add support for 400Gbps (50Gbps per lane) link modesJiri Pirko1-1/+9
Add support for 400Gbps speed, link modes of 50Gbps per lane Signed-off-by: Jiri Pirko <[email protected]> Signed-off-by: Ido Schimmel <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-10-04net: phy: extract pause modeRussell King1-7/+13
Extract the update of phylib's software pause mode state from genphy_read_status(), so that we can re-use this functionality with PHYs that have alternative ways to read the negotiation results. Tested-by: tinywrkb <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: Russell King <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-08-13net: phy: add phy_speed_down_core and phy_resolve_min_speedHeiner Kallweit1-0/+28
phy_speed_down_core provides most of the functionality for phy_speed_down. It makes use of new helper phy_resolve_min_speed that is based on the sorting of the settings[] array. In certain cases it may be helpful to be able to exclude legacy half duplex modes, therefore prepare phy_resolve_min_speed() for it. v2: - rename __phy_speed_down to phy_speed_down_core Signed-off-by: Heiner Kallweit <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2019-08-13net: phy: add __set_linkmode_max_speedHeiner Kallweit1-2/+7
We will need the functionality of __set_linkmode_max_speed also for linkmode bitmaps other than phydev->supported. Therefore split it. v2: - remove unused parameter from __set_linkmode_max_speed Signed-off-by: Heiner Kallweit <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2019-08-11net: phy: add phy_modify_paged_changedHeiner Kallweit1-5/+24
Add helper function phy_modify_paged_changed, behavios is the same as for phy_modify_changed. Signed-off-by: Heiner Kallweit <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-05-22net: phy: Add support for 100BaseT1 and 1000BaseT1Andrew Lunn1-1/+3
Add link modes for 100Mbps and 1Gbps over a single pair. Signed-off-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-05-04net: phy: improve pause handlingHeiner Kallweit1-1/+1
When probing the phy device we set sym and asym pause in the "supported" bitmap (unless the PHY tells us otherwise). However we don't know yet whether the MAC supports pause. Simply copying phy->supported to phy->advertising will trigger advertising pause, and that's not what we want. Therefore add phy_advertise_supported() that copies all modes but doesn't touch the pause bits. In phy_support_(a)sym_pause we shouldn't set any bits in the supported bitmap because we may set a bit the PHY intentionally disabled. Effective pause support should be the AND-combined PHY and MAC pause capabilities. If the MAC supports everything, then it's only relevant what the PHY supports. If MAC supports sym pause only, then we have to clear the asym bit in phydev->supported. Copy the pause flags only and don't touch the modes, because a driver may have intentionally removed a mode from phydev->advertising. Signed-off-by: Heiner Kallweit <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-04-14phy: warn if phylib and ethtool PHY mode definitions are out of syncHeiner Kallweit1-0/+5
If new PHY modes are added people may miss to update all relevant places in the kernel. Therefore add a build bug check for new modes in enum ethtool_link_mode_bit_indices that haven't been added to phylib yet. Suggested-by: Andrew Lunn <[email protected]> Signed-off-by: Heiner Kallweit <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-04-14net: phy: add support for new modes in phylibHeiner Kallweit1-0/+18
Recently new modes have been added to ethtool.h, but the related extension to phylib hasn't been done yet. So add support for these modes. v2: - add missing 100Gbps and 50Gbps modes Signed-off-by: Heiner Kallweit <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-04-14net: phy: shrink PHY settings arrayHeiner Kallweit1-202/+45
The definition of array settings[] is quite lengthy meanwhile. Add a macro to shrink the definition. v2: - Fix an indentation issue Signed-off-by: Heiner Kallweit <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-17net: phy: improve phy_resolve_aneg_linkmodeHeiner Kallweit1-36/+7
We have the settings array of modes which is sorted based on aneg priority. Instead of checking each mode manually let's simply iterate over the sorted settings. Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-13net: phy: Move of_set_phy_eee_broken to phy-core.cMaxime Chevallier1-0/+27
Since of_set_phy_supported was moved to phy-core.c, we can also move of_set_phy_eee_broken to the same location, so that we have all OF functions in the same place. This patch doesn't intend to introduce any change in behaviour. Signed-off-by: Maxime Chevallier <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-13net: phy: Mask-out non-compatible modes when setting the max-speedMaxime Chevallier1-0/+45
When setting a PHY's max speed using either the max-speed DT property or ethtool, we should mask-out all non-compatible modes according to the settings table, instead of just the 10/100BASET modes. Signed-off-by: Maxime Chevallier <[email protected]> Suggested-by: Russell King <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-10net: phy: add register modifying helpers returning 1 on changeHeiner Kallweit1-9/+118
When modifying registers there are scenarios where we need to know whether the register content actually changed. This patch adds new helpers to not break users of the current ones, phy_modify() etc. Signed-off-by: Heiner Kallweit <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-06net: phy: provide full set of accessor functions to MMD registersNikita Yushchenko1-13/+103
This adds full set of locked and unlocked accessor functions to read and write PHY MMD registers and/or bitfields. Set of functions exactly matches what is already available for PHY legacy registers. Signed-off-by: Nikita Yushchenko <[email protected]> Signed-off-by: Andrew Lunn <[email protected]> Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-01-22net: phy: Convert some PHY and MDIO driver files to SPDX headersAndrew Lunn1-5/+1
Where the license text and the MODULE_LICENSE() value agree, convert to using an SPDX header, removing the license text. Signed-off-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2018-11-11net: phy: Add support for resolving 5G and 2.5G autonegAndrew Lunn1-0/+8
Now that 2.5G and 5G can be represented in phydev->advertising and phydev->lp_advertising, add these two links modes as possible resolutions to auto negotiation. Signed-off-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2018-11-11net: phy: Add more link modes to the settings tableAndrew Lunn1-4/+158
Now that PHYs and MAC can support more than 32 bit masks, add link modes which are > 31 to the PHY settings table. Signed-off-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2018-11-11net: phy: Convert u32 phydev->lp_advertising to linkmodeAndrew Lunn1-7/+6
Convert phy drivers to report the link partner advertised modes using a linkmode bitmap. This allows them to report the higher speeds which don't fit in a u32. Signed-off-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2018-11-11net: ethernet: Convert phydev advertize and supported from u32 to link modeAndrew Lunn1-14/+24
There are a few MAC/PHYs combinations which now support > 1Gbps. These may need to make use of link modes with bits > 31. Thus their supported PHY features or advertised features cannot be implemented using the current bitmap in a u32. Convert to using a linkmode bitmap, which can support all the currently devices link modes, and is future proof as more modes are added. Signed-off-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2018-03-04net: phy: Fix spelling mistake: "advertisment"-> "advertisement"Colin Ian King1-2/+2
Trivial fix to spelling mistake in comments and error message text. Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2018-01-15net: phy: Have __phy_modify return 0 on successAndrew Lunn1-7/+6
__phy_modify would return the old value of the register before it was modified. Thus on success, it does not return 0, but a positive value. Thus functions using phy_modify, which is a wrapper around __phy_modify, can start returning > 0 on success, rather than 0. As a result, breakage has been noticed in various places, where 0 was assumed. Code inspection does not find any current location where the return of the old value is currently used. So have __phy_modify return 0 on success. When there is a real need for the old value, either a new accessor can be added, or an additional parameter passed. Fixes: fea23fb591cc ("net: phy: convert read-modify-write to phy_modify()") Fixes: 2b74e5be17d2 ("net: phy: add phy_modify() accessor") Reported-by: Geert Uytterhoeven <[email protected]> Tested-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Andrew Lunn <[email protected]> Tested-by: Niklas Cassel <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2018-01-08net: phy: fix wrong masks to phy_modify()Russell King1-1/+1
The mask argument for phy_modify() in several locations was inverted. Fixes: fea23fb591cc ("net: phy: convert read-modify-write to phy_modify()") Reported-by: Heiner Kallweit <[email protected]> Tested-by: Andrew Lunn <[email protected]> Signed-off-by: Russell King <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2018-01-03net: phy: add phy_modify() accessorRussell King1-0/+23
Add phy_modify() convenience accessor to complement the mdiobus counterpart. Signed-off-by: Russell King <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2018-01-03net: phy: add paged phy register accessorsRussell King1-0/+157
Add a set of paged phy register accessors which are inherently safe in their design against other accesses interfering with the paged access. Signed-off-by: Russell King <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2018-01-03net: phy: add unlocked accessorsRussell King1-0/+25
Add unlocked versions of the bus accessors, which allows access to the bus with all the tracing. These accessors validate that the bus mutex is held, which is a basic requirement for all mii bus accesses. Also added is a read-modify-write unlocked accessor with the same locking requirements. Signed-off-by: Russell King <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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