| Age | Commit message (Collapse) | Author | Files | Lines |
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Selecting CONFIG_OMAP2PLUS_MBOX while compile testing
causes a build failure:
WARNING: unmet direct dependencies detected for OMAP2PLUS_MBOX
Depends on [n]: MAILBOX [=y] && (ARCH_OMAP2PLUS || ARCH_K3)
Selected by [m]:
- TI_K3_M4_REMOTEPROC [=m] && REMOTEPROC [=y] && (ARCH_K3 || COMPILE_TEST [=y])
Using 'select' to force-enable another subsystem is generally
a mistake and causes problems such as this one, so change the
three drivers that link against this driver to use 'depends on'
instead, and ensure the driver itself can be compile tested
regardless of the platform.
When compile-testing without CONFIG_TI_SCI_PROTOCOL=m, there
is a chance for a link failure, so add a careful dependency
on that.
arm-linux-gnueabi-ld: drivers/remoteproc/ti_k3_m4_remoteproc.o: in function `k3_m4_rproc_probe':
ti_k3_m4_remoteproc.c:(.text.k3_m4_rproc_probe+0x76): undefined reference to `devm_ti_sci_get_by_phandle'
Fixes: ebcf9008a895 ("remoteproc: k3-m4: Add a remoteproc driver for M4F subsystem")
Signed-off-by: Arnd Bergmann <[email protected]>
Reviewed-by: Mathieu Poirier <[email protected]>
Reviewed-by: Andrew Davis <[email protected]>
Reviewed-by: Martyn Welch <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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The ARM MHUv3 controller is only present on ARM64 SoCs. Hence add a
dependency on ARM64, to prevent asking the user about this driver when
configuring a kernel for a different architecture than ARM64.
Fixes: ca1a8680b134b5e6 ("mailbox: arm_mhuv3: Add driver")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Acked-by: Sudeep Holla <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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This newly added driver fails compile testing on 32-bit architectures
because it relies on 64-bit MMIO register access:
drivers/mailbox/qcom-cpucp-mbox.c: In function 'qcom_cpucp_mbox_irq_fn':
drivers/mailbox/qcom-cpucp-mbox.c:54:18: error: implicit declaration of function 'readq'; did you mean 'readb'? [-Wimplicit-function-declaration]
54 | status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT);
| ^~~~~
| readb
drivers/mailbox/qcom-cpucp-mbox.c:65:17: error: implicit declaration of function 'writeq'; did you mean 'writeb'? [-Wimplicit-function-declaration]
65 | writeq(BIT(i), cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR);
| ^~~~~~
| writeb
Change the Kconfig dependency to disallow that configuration as well.
Fixes: 0e2a9a03106c ("mailbox: Add support for QTI CPUCP mailbox controller")
Signed-off-by: Arnd Bergmann <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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Add support for CPUSS Control Processor (CPUCP) mailbox controller,
this driver enables communication between AP and CPUCP by acting as
a doorbell between them.
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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Add support for ARM MHUv3 mailbox controller.
Support is limited to the MHUv3 Doorbell extension using only the PBX/MBX
combined interrupts.
Signed-off-by: Cristian Marussi <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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The kernel FIFO queue has a couple issues. The biggest issue is that
it causes extra latency in a path that can be used in real-time tasks,
such as communication with real-time remote processors.
The whole FIFO idea itself looks to be a leftover from before the
unified mailbox framework. The current mailbox framework expects
mbox_chan_received_data() to be called with data immediately as it
arrives. Remove the FIFO and pass the messages to the mailbox
framework directly as part of a threaded IRQ handler.
Signed-off-by: Andrew Davis <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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This driver is now orphaned and superseded by
drivers/soc/apple/mailbox.c.
Acked-by: Eric Curtin <[email protected]>
Acked-by: Neal Gompa <[email protected]>
Acked-by: Alyssa Rosenzweig <[email protected]>
Signed-off-by: Hector Martin <[email protected]>
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git://git.linaro.org/landing-teams/working/fujitsu/integration
Pull mailbox updates from Jassi Brar:
- mailbox api: allow direct registration to a channel and convert omap
and pcc to use mbox_bind_client
- omap and hi6220 : use of_property_read_bool
- test: fix double-free and use spinlock header
- rockchip and bcm-pdc: drop of_match_ptr
- mpfs: change config symbol
- mediatek gce: support MT6795
- qcom apcs: consolidate of_device_id and support IPQ9574
* tag 'mailbox-v6.4' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
dt-bindings: mailbox: qcom: add compatible for IPQ9574 SoC
mailbox: qcom-apcs-ipc: do not grow the of_device_id
dt-bindings: mailbox: qcom,apcs-kpss-global: use fallbacks for few variants
dt-bindings: mailbox: mediatek,gce-mailbox: Add support for MT6795
mailbox: mpfs: convert SOC_MICROCHIP_POLARFIRE to ARCH_MICROCHIP_POLARFIRE
mailbox: bcm-pdc: drop of_match_ptr for ID table
mailbox: rockchip: drop of_match_ptr for ID table
mailbox: mailbox-test: Fix potential double-free in mbox_test_message_write()
mailbox: mailbox-test: Explicitly include header for spinlock support
mailbox: Use of_property_read_bool() for boolean properties
mailbox: pcc: Use mbox_bind_client
mailbox: omap: Use mbox_bind_client
mailbox: Allow direct registration to a channel
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As part of converting RISC-V SOC_FOO symbols to ARCH_FOO to match the
use of such symbols on other architectures, convert the Microchip FPGA
mailbox driver to use the new symbol.
Signed-off-by: Conor Dooley <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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This driver has a MODULE_LICENSE but is not tristate so cannot be
built as a module, unlike all its peers: make it modular to match.
Signed-off-by: Nick Alcock <[email protected]>
Suggested-by: Michal Simek <[email protected]>
Cc: Luis Chamberlain <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Hitomi Hasegawa <[email protected]>
Cc: Jassi Brar <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: [email protected]
Signed-off-by: Luis Chamberlain <[email protected]>
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git://git.linaro.org/landing-teams/working/fujitsu/integration
Pull mailbox updates from Jassi Brar:
- qcom: enable sc8280xp, sm8550 and sm4250 support
- ti: default to ARCH_K3 for msg manager
- mediatek:
- add mt8188 and mt8186 support
- request irq only after got ready
- zynq-ipi: fix error handling after device_register
- mpfs: check sys-con status
- rockchip: simplify by using device_get_match_data
* tag 'mailbox-v6.2' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
dt-bindings: mailbox: qcom-ipcc: Add compatible for SM8550
mailbox: mtk-cmdq: Do not request irq until we are ready
mailbox: zynq-ipi: fix error handling while device_register() fails
mailbox: mtk-cmdq-mailbox: Use platform data directly instead of copying
mailbox: arm_mhuv2: Fix return value check in mhuv2_probe()
dt-bindings: mailbox: mediatek,gce-mailbox: add mt8188 compatible name
dt-bindings: mailbox: add GCE header file for mt8188
mailbox: mpfs: read the system controller's status
mailbox: mtk-cmdq: add MT8186 support
mailbox: mtk-cmdq: add gce ddr enable support flow
mailbox: mtk-cmdq: add gce software ddr enable private data
mailbox: mtk-cmdq: Use GCE_CTRL_BY_SW definition instead of number
mailbox: rockchip: Use device_get_match_data() to simplify the code
dt-bindings: mailbox: qcom-ipcc: Add sc8280xp compatible
mailbox: config: ti-msgmgr: Default set to ARCH_K3 for TI msg manager
mailbox: qcom-apcs-ipc: Add SM4250 APCS IPC support
dt-bindings: mailbox: qcom: Add SM4250 APCS compatible
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Defaulting the build to ARCH_K3 for the TI message manager driver.
Signed-off-by: Nicolas Frayer <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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Adjust to reality and remove another layer of pointless Kconfig
indirection. CONFIG_GENERIC_MSI_IRQ is good enough to serve
all purposes.
Signed-off-by: Thomas Gleixner <[email protected]>
Reviewed-by: Jason Gunthorpe <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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This patch is to for MediaTek ADSP IPC mailbox controller driver
It is used to send short messages between processors with adsp
Signed-off-by: Allen-KH Cheng <[email protected]>
Reviewed-by: Tzung-Bi Shih <[email protected]>
Reviewed-by: YC Hung <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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Apple SoCs such as the M1 come with various co-processors. Mailboxes
are used to communicate with those. This driver adds support for
two variants of those mailboxes.
Signed-off-by: Sven Peter <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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This patch enables the qcom_ipcc driver to be loaded as a
module. IPCC is fairly core to system, so as such it should
never be unloaded. It registers as a mailbox + irq controller
and the irq controller drivers in kernel are not supposed to
be unloaded as they don't have the visibility over the clients
consuming the irqs. Hence adding supress_bind_attrs to disable
bind/unbind via sysfs.
Signed-off-by: Amit Pundir <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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This driver adds support for the single mailbox channel of the MSS
system controller on the Microchip PolarFire SoC.
Signed-off-by: Conor Dooley <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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Fix trivial typos in mailbox driver comments.
s/Intergrated/Integrated/
s/extenstion/extension/
s/atleast/at least/
s/commnunication/communication/
s/assgined/assigned/
s/commnunication/communication/
s/recevied/received/
s/succeded/succeeded/
s/implmentation/implementation/
s/definiation/definition/
s/traget/target/
s/wont/won't/
Cc: [email protected]
Signed-off-by: Tom Saeger <[email protected]>
Reviewed-by: Randy Dunlap <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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This adds driver for the ARM MHUv2 (Message Handling Unit) mailbox
controller.
This is based on the accepted DT bindings of the controller and supports
combination of both transport protocols, i.e. doorbell and data-transfer.
Transmitting and receiving data through the mailbox framework is done
through struct arm_mhuv2_mbox_msg.
Based on the initial work done by Morten Borup Petersen from ARM.
Co-developed-by: Tushar Khandelwal <[email protected]>
Signed-off-by: Tushar Khandelwal <[email protected]>
Tested-by: Usama Arif <[email protected]>
Signed-off-by: Viresh Kumar <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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This allows compiling the driver on architectures where the hardware is not
available. Most other mailbox drivers support this as well.
Signed-off-by: Martin Kaiser <[email protected]>
Reviewed-by: Fabien Dessenne <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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Add support for the Inter-Processor Communication Controller (IPCC)
block from Qualcomm that coordinates the interrupts (inbound & outbound)
for Multiprocessor (MPROC), COMPUTE-Level0 (COMPUTE-L0) & COMPUTE-Level1
(COMPUTE-L1) protocols for the Application Processor Subsystem (APSS).
This driver is modeled as an irqchip+mailbox driver. The irqchip part
helps in receiving the interrupts from the IPCC clients such as modems,
DSPs, PCI-E etc... and forwards them to respective entities in APSS.
On the other hand, the mailbox part is used to send interrupts to the IPCC
clients from the entities of APSS.
Reviewed-by: Bjorn Andersson <[email protected]>
Signed-off-by: Raghavendra Rao Ananta <[email protected]>
Signed-off-by: Venkata Narendra Kumar Gutta <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
[mani: moved to mailbox, added static mbox channels and cleanups]
Signed-off-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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The Spreadtrum mailbox controller supports 8 channels to communicate
with MCUs, and it contains 2 different parts: inbox and outbox, which
are used to send and receive messages by IRQ mode.
Signed-off-by: Baolin Wang <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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Allwinner sun6i, sun8i, sun9i, and sun50i SoCs contain a hardware
message box used for communication between the ARM CPUs and the ARISC
management coprocessor. This mailbox contains 8 unidirectional
4-message FIFOs.
Add a driver for it, so it can be used with the Linux mailbox framework.
Reviewed-by: Philipp Zabel <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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The TI K3 AM65x and J721E family of SoCs have a new Mailbox IP that
is based on the existing Mailbox IP present in OMAP architecture based
SoCs. Each instance of the legacy OMAP Mailbox IP is now a single cluster
within the newer Mailbox IP instance on K3 architecture based SoCs. A
single K3 Mailbox IP instance has multiple clusters with each cluster
providing the same functionality as the existing OMAP Mailbox IP.
Reuse the existing OMAP Mailbox driver to extend the support for this
newer IP present within the Main NavSS block on K3 SoCs. The K3 family
of SoCs use 64-bit ARMv8 processors for running Linux, so the driver is
also enhanced to deal with the differences between the 32-bit message
payloads and the 64-bit pointers used by the client drivers.
Signed-off-by: Suman Anna <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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Add SPDX license identifiers to all Make/Kconfig files which:
- Have no license information of any form
These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:
GPL-2.0-only
Signed-off-by: Thomas Gleixner <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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This adds support for the mailbox via which the kernel can communicate
with the firmware running on the secure processor of the Armada 37xx
SOC.
The rWTM secure processor has access to internal eFuses and
cryptographic circuits, such as the Entropy Bit Generator to generate
true random numbers.
Signed-off-by: Marek Behun <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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This patch is to introduce ZynqMP IPI mailbox controller driver
to use the ZynqMP IPI block as mailboxes.
Signed-off-by: Wendy Liang <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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ti-msgmr driver can support K3 platforms as well.
Signed-off-by: Nishanth Menon <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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The i.MX Messaging Unit is a two side block which allows applications
implement communication over this sides.
The MU includes the following features:
- Messaging control by interrupts or by polling
- Four general-purpose interrupt requests reflected to the other side
- Three general-purpose flags reflected to the other side
- Four receive registers with maskable interrupt
- Four transmit registers with maskable interrupt
Reviewed-by: Vladimir Zapolskiy <[email protected]>
Reviewed-by: Dong Aisheng <[email protected]>
Signed-off-by: Oleksij Rempel <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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This patch is first version of Mediatek Command Queue(CMDQ) driver. The
CMDQ is used to help write registers with critical time limitation,
such as updating display configuration during the vblank. It controls
Global Command Engine (GCE) hardware to achieve this requirement.
Currently, CMDQ only supports display related hardwares, but we expect
it can be extended to other hardwares for future requirements.
Signed-off-by: Houlong Wei <[email protected]>
Signed-off-by: HS Liao <[email protected]>
Signed-off-by: CK Hu <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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The current defconfig is inconsistent as it selects the mailbox and
the clock for the hi6220 and the hi3660 without having their Kconfigs
making sure the dependencies are correct. It ends up when selecting
different versions for the kernel (for example when git bisecting)
those options disappear and they don't get back, leading to unexpected
behaviors. In our case, the cpufreq driver does no longer work because
the clock fails to initialize due to the clock stub and the mailbox
missing.
In order to have the dependencies correctly set when defaulting, let's
do the same as commit 3a49afb84ca074e ("clk: enable hi655x common clk
automatically") where we select automatically the driver when the
parent driver is selected. With sensible defaults in place, we can leave
other choices for EXPERT.
Signed-off-by: Daniel Lezcano <[email protected]>
Signed-off-by: Leo Yan <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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The STMicroelectronics STM32 Inter-Processor Communication Controller
(IPCC) is used for communicating data between two processors.
It provides a non blocking signaling mechanism to post and retrieve
communication data in an atomic way.
Signed-off-by: Fabien Dessenne <[email protected]>
Signed-off-by: Ludovic Barre <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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Remove dependencies on HAS_DMA where a Kconfig symbol depends on another
symbol that implies HAS_DMA, and, optionally, on "|| COMPILE_TEST".
In most cases this other symbol is an architecture or platform specific
symbol, or PCI.
Generic symbols and drivers without platform dependencies keep their
dependencies on HAS_DMA, to prevent compiling subsystems or drivers that
cannot work anyway.
This simplifies the dependencies, and allows to improve compile-testing.
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Mark Brown <[email protected]>
Acked-by: Robin Murphy <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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Hi3660 mailbox controller is used to send message within multiple
processors, MCU, HIFI, etc. It supports 32 mailbox channels and every
channel can only be used for single transferring direction. Once the
channel is enabled, it needs to specify the destination interrupt and
acknowledge interrupt, these two interrupt vectors are used to create
the connection between the mailbox and interrupt controllers.
The data transferring supports two modes, one is named as "automatic
acknowledge" mode so after send message the kernel doesn't need to wait
for acknowledge from remote and directly return; there have another mode
is to rely on handling interrupt for acknowledge.
This commit is for initial version driver, which only supports
"automatic acknowledge" mode to support CPU clock, which is the only
one consumer to use mailbox and has been verified. Later may enhance
this driver for interrupt mode (e.g. for supporting HIFI).
Signed-off-by: Leo Yan <[email protected]>
Signed-off-by: Ruyi Wang <[email protected]>
Signed-off-by: Kaihua Zhong <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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With the addition of the ARCH_TEGRA_194_SOC driver, we get a new Kconfig warning:
warning: (ARCH_TEGRA_186_SOC && ARCH_TEGRA_194_SOC) selects TEGRA_HSP_MBOX which has unmet direct dependencies (MAILBOX && ARCH_TEGRA_186_SOC)
It looks like the dependency is a bit too strict here, allowing the driver to
be built for any Tegra chip avoids the problem.
Fixes: 6f9ed07fde03 ("soc/tegra: Add Tegra194 SoC configuration option")
Signed-off-by: Arnd Bergmann <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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By default, we build Broadcom FlexRM driver as loadable module for
iProc SOCs so that kernel image is little smaller and we load FlexRM
driver only when required.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Scott Branden <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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The Broadcom FlexRM Mailbox is only present in the Broadcom IPROC SoCs.
Add depends on ARCH_BCM_IPROC to BCM_FLEXRX_MBOX.
Signed-off-by: Scott Branden <[email protected]>
Reviewed-by: Ray Jui <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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This implements a driver that exposes the IPC bits found in the APCS
Global block in various Qualcomm platforms. The bits are used to signal
inter-processor communication signals from the application CPU to other
masters.
Signed-off-by: Bjorn Andersson <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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The Broadcom FlexRM mailbox driver uses platform MSI support but
not all ARCHs provide asm/msi.h. Due to this, we get compilation
error in Broadcom FlexRM mailbox driver via linux/msi.h on ARCHs
which lack asm/msi.h.
This patch removes "depends on COMPILE_TEST" for Kconfig option
BCM_FLEXRM_MBOX so that Broadcom FlexRM mailbox driver is only
compiled for ARM64.
Signed-off-by: Anup Patel <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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Some of the Broadcom iProc SoCs have FlexRM ring manager
which provides a ring-based programming interface to various
offload engines (e.g. RAID, Crypto, etc).
This patch adds a common mailbox driver for Broadcom FlexRM
ring manager which can be shared by various offload engine
drivers (implemented as mailbox clients).
Reviewed-by: Ray Jui <[email protected]>
Reviewed-by: Scott Branden <[email protected]>
Reviewed-by: Pramod KUMAR <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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Adds support for Northstar Plus (NS+) products to the PDC mailbox
driver. The PDC driver was originally written to support the PDC
ring manager in the Northstar2 (64-bit) device. The NS+ (32 bit
device) uses an almost identical ring manager, though with a
different name. We just need to check for the type of hardware in
use, in order to write the appropriate interrupt configuration register.
Also updated DMA width to be correct for both NS+ and NS2.
Tested on NS+ and NS2.
Signed-off-by: Steve Lin <[email protected]>
Acked-by: Jon Mason <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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This driver exposes a mailbox interface for interprocessor communication
using the Hardware Synchronization Primitives (HSP) module's doorbell
mechanism. There are multiple HSP instances and they provide additional
features such as shared mailboxes, shared and arbitrated semaphores.
A driver for a remote processor can use the mailbox client provided by
the HSP driver and build an IPC protocol on top of this synchronization
mechanism.
Based on work by Joseph Lo <[email protected]>.
Acked-by: Jassi Brar <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Add Message-Handling-Unit driver for platform variants as mailbox controller.
Actually, only the Amlogic Meson GXBB SoC MHU is supported.
Signed-off-by: Neil Armstrong <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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Add HAS_DMA Kconfig dependency to BCM_PDC_MBOX to avoid link
error on some platforms.
Reported-by: Fengguang Wu <[email protected]>
Signed-off-by: Rob Rice <[email protected]>
Acked-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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The Broadcom PDC mailbox driver is a mailbox controller that
manages data transfers to and from one or more offload engines.
Signed-off-by: Rob Rice <[email protected]>
Reviewed-by: Scott Branden <[email protected]>
Reviewed-by: Ray Jui <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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Support for TI Message Manager Module. This hardware block manages a
bunch of hardware queues meant for communication between processor
entities.
Clients sitting on top of this would manage the required protocol
for communicating with the counterpart entities.
For more details on TI Message Manager hardware block, see documentation
that will is available here: http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf
Chapter 8.1(Message Manager)
Signed-off-by: Nishanth Menon <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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This driver is found on RK3368 SoCs.
The Mailbox module is a simple APB peripheral that allows both
the Cortex-A53 MCU system to communicate by writing operation to
generate interrupt.
The registers are accessible by both CPU via APB interface.
The Mailbox has the following main features:
1) Support dual-core system: Cortex-A53 and MCU.
2) Support APB interface.
3) Support four mailbox elements, each element includes one data word,
one command word register and one flag bit that can represent
one interrupt.
4) Four interrupts to Cortex-A53.
5) Four interrupts to MCU.
6) Provide 32 lock registers for software to use to indicate whether
mailbox is occupied.
[Jassi: Removed unused variable buf_base]
Signed-off-by: Caesar Wang <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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Add driver for Hi6220 mailbox, the mailbox communicates with MCU; for
sending data, it can support two methods for low level implementation:
one is to use interrupt as acknowledge, another is automatic mode which
without any acknowledge. These two methods have been supported in the
driver. For receiving data, it will depend on the interrupt to notify
the channel has incoming message.
Now mailbox driver is used to send message to MCU to control dynamic
voltage and frequency scaling for CPU, GPU and DDR.
Signed-off-by: Leo Yan <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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X-Gene mailbox controller provides 8 mailbox channels, with
each channel has a dedicated interrupt line.
Signed-off-by: Feng Kan <[email protected]>
Signed-off-by: Duc Dang <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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Not every arch has io memory.
So, unbreak the build by fixing the dependencies.
Signed-off-by: Richard Weinberger <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>
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