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path: root/drivers/gpu
AgeCommit message (Expand)AuthorFilesLines
2024-04-04drm/xe: Rework rebindingThomas Hellström5-51/+14
2024-04-04drm/xe: Use ring ops TLB invalidation for rebindsThomas Hellström6-9/+30
2024-04-04drm/mediatek: ovl_adaptor: drop driver owner initializationKrzysztof Kozlowski1-1/+0
2024-04-04drm/i915: Optimize out redundant dbuf slice updatesVille Syrjälä1-9/+18
2024-04-04drm/mediatek: ovl: drop driver owner initializationKrzysztof Kozlowski1-1/+0
2024-04-04drm/i915: Use a plain old int for the cdclk/mdclk ratioVille Syrjälä4-9/+13
2024-04-04drm/mediatek: merge: drop driver owner initializationKrzysztof Kozlowski1-1/+0
2024-04-04drm/i915: Implement vblank synchronized MBUS join changesStanislav Lisovskiy3-38/+92
2024-04-04drm/mediatek: gamma: drop driver owner initializationKrzysztof Kozlowski1-1/+0
2024-04-04drm/i915: Use the correct mdclk/cdclk ratio in MBUS updatesVille Syrjälä3-11/+20
2024-04-04drm/i915: Use old mbus_join value when increasing CDCLKStanislav Lisovskiy1-0/+6
2024-04-04drm/mediatek: color: drop driver owner initializationKrzysztof Kozlowski1-1/+0
2024-04-04drm/i915: Add debugs for mbus joining and dbuf ratio programmingVille Syrjälä1-0/+9
2024-04-04drm/i915: Extract intel_dbuf_mdclk_min_tracker_update()Ville Syrjälä1-18/+25
2024-04-04drm/i915: Extract intel_dbuf_mbus_join_update()Ville Syrjälä1-11/+24
2024-04-04drm/i915: Relocate intel_mbus_dbox_update()Ville Syrjälä1-83/+83
2024-04-04drm/i915: Loop over all active pipes in intel_mbus_dbox_updateStanislav Lisovskiy1-6/+1
2024-04-04drm/mediatek: ccorr: drop driver owner initializationKrzysztof Kozlowski1-1/+0
2024-04-04drm/i915/cdclk: Indicate whether CDCLK change happens during pre or post plan...Ville Syrjälä1-13/+6
2024-04-04drm/i915/cdclk: Drop tgl/dg2 cdclk bump hacksVille Syrjälä1-19/+0
2024-04-04drm/mediatek: aal: drop driver owner initializationKrzysztof Kozlowski1-1/+0
2024-04-04drm/i915/cdclk: Fix voltage_level programming edge caseVille Syrjälä1-10/+27
2024-04-04drm/i915/cdclk: Fix CDCLK programming order when pipes are activeVille Syrjälä2-2/+8
2024-04-04drm/bridge: adv7511: Allow IRQ to share GPIO pinsAdam Ford1-1/+7
2024-04-04drm/i915/display: Read/Write Adaptive Sync SDPMitul Golani2-0/+2
2024-04-04drm/i915/display: Compute vrr_vsync paramsMitul Golani4-2/+41
2024-04-04drm/i915/display: Add state checker for Adaptive Sync SDPMitul Golani1-0/+46
2024-04-04drm/i915/display: Compute AS SDP parametersMitul Golani1-0/+24
2024-04-04drm/i915/dp: Add wrapper function to check AS SDPMitul Golani2-0/+9
2024-04-04drm/i915/dp: Add Read/Write support for Adaptive Sync SDPMitul Golani4-1/+114
2024-04-04drm/i915/display: Add crtc state dump for Adaptive Sync SDPMitul Golani2-0/+4
2024-04-04drm/dp: Add Adaptive Sync SDP loggingMitul Golani1-0/+12
2024-04-04drm/dp: Add support to indicate if sink supports AS SDPMitul Golani1-0/+25
2024-04-03drm/xe/xe_migrate: Cast to output precision before multiplying operandsHimal Prasad Ghimiray1-4/+4
2024-04-03drm/i915/guc: Remove bogus null checkRodrigo Vivi1-1/+1
2024-04-03drm/i915/mst: Reject FEC+MST on ICLVille Syrjälä1-1/+2
2024-04-03drm/i915/mst: Limit MST+DSC to TGL+Ville Syrjälä2-1/+2
2024-04-03drm/i915/dp: Fix the computation for compressed_bpp for DISPLAY < 13Ankit Nautiyal1-2/+3
2024-04-03drm/i915/gt: Enable only one CCS for compute workloadAndi Shyti5-0/+65
2024-04-03drm/i915/gt: Do not generate the command streamer for all the CCSAndi Shyti1-0/+17
2024-04-03drm/i915/gt: Disable HW load balancing for CCSAndi Shyti2-2/+22
2024-04-03drm/i915/gt: Limit the reserved VM space to only the platforms that need itAndi Shyti3-4/+14
2024-04-03drm/i915/psr: Fix intel_psr2_sel_fetch_et_alignment usageJouni Högander1-22/+33
2024-04-03drm/i915/psr: Move writing early transport pipe srcJouni Högander2-9/+7
2024-04-03drm/i915/psr: Calculate PIPE_SRCSZ_ERLY_TPT valueJouni Högander2-0/+18
2024-04-03drm/xe: Use ordered wq for preempt fence waitingMatthew Brost3-2/+14
2024-04-03drm/i915: Use debugfs_create_bool() for "i915_bigjoiner_force_enable"Ville Syrjälä1-42/+2
2024-04-03drm/i915/mst: Reject FEC+MST on ICLVille Syrjälä1-1/+2
2024-04-03drm/i915/mst: Limit MST+DSC to TGL+Ville Syrjälä2-1/+2
2024-04-03drm/i915: Extract glk_need_scaler_clock_gating_wa()Ville Syrjälä1-6/+10
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