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path: root/drivers/gpu
AgeCommit message (Expand)AuthorFilesLines
2024-05-06drm/i915: pass dev_priv explicitly to ALPM_CTLJani Nikula2-3/+3
2024-05-06drm/i915: pass dev_priv explicitly to PIPE_SRCSZ_ERLY_TPTJani Nikula3-3/+3
2024-05-06drm/i915: pass dev_priv explicitly to PSR2_MAN_TRK_CTLJani Nikula2-9/+16
2024-05-06drm/i915: pass dev_priv explicitly to PSR2_SU_STATUSJani Nikula2-3/+4
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR2_STATUSJani Nikula2-5/+6
2024-05-06drm/i915: pass dev_priv explicitly to PSR_EVENTJani Nikula2-2/+4
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR2_CTLJani Nikula2-7/+10
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_DEBUGJani Nikula2-2/+2
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_PERF_CNTJani Nikula2-2/+2
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_STATUSJani Nikula2-2/+2
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_DATAJani Nikula2-2/+2
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_CTLJani Nikula2-2/+2
2024-05-06drm/i915: pass dev_priv explicitly to TRANS_PSR_IIRJani Nikula3-5/+9
2024-05-06drm/i915: pass dev_priv explicitly to TRANS_PSR_IMRJani Nikula3-3/+5
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_CTLJani Nikula2-2/+2
2024-05-06drm/i915: pass dev_priv explicitly to TRANS_EXITLINEJani Nikula2-3/+6
2024-05-05drm/msm: Add devcoredump support for a750Connor Abbott1-18/+46
2024-05-05drm/msm: Adjust a7xx GBIF debugbus dumpingConnor Abbott2-4/+4
2024-05-04drm/msm: Update a6xx registers XMLConnor Abbott1-3/+44
2024-05-04drm/msm: Fix imported a750 snapshot header for upstreamConnor Abbott1-434/+454
2024-05-04drm/msm: Import a750 snapshot registers from kgslConnor Abbott1-0/+1426
2024-05-04drm/msm/a6xx: Avoid a nullptr dereference when speedbin setting failsKonrad Dybcio1-1/+2
2024-05-04drm/msm/adreno: fix CP cycles stat retrieval on a7xxZan Dobersek1-2/+2
2024-05-04drm/msm/a7xx: allow writing to CP_BV counter selection registersZan Dobersek1-4/+4
2024-05-03drm/xe: Demote CCS_MODE info to debug onlyRodrigo Vivi1-2/+2
2024-05-03drm/xe/bmg: Enable the display supportBalasubramani Vivekanandan1-0/+1
2024-05-03drm/i915/display: perform transient flushMatthew Auld5-1/+45
2024-05-03drm/xe/device: implement transient flushNirmoy Das3-0/+54
2024-05-03drm/xe/gt_print: add xe_gt_err_once()Matthew Auld1-0/+3
2024-05-03drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5Balasubramani Vivekanandan1-0/+3
2024-05-03Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping"Ankit Nautiyal1-3/+2
2024-05-03drm/i915/bmg: BMG should re-use MTL's south display logicMatt Roper1-2/+2
2024-05-03drm/i915/xe2hpd: Do not program MBUS_DBOX BW creditsJosé Roberto de Souza1-1/+1
2024-05-03drm/i915/xe2hpd: Add max memory bandwidth algorithmMatt Roper4-2/+69
2024-05-03drm/i915/xe2hpd: Configure CHICKEN_MISC_2 before enabling planesAnusha Srivatsa2-0/+5
2024-05-03drm/i915/xe2hpd: Add display infoLucas De Marchi1-0/+7
2024-05-03drm/i915/xe2hpd: update pll values in sync with BspecRavi Kumar Vodapalli1-2/+44
2024-05-03drm/i915/xe2hpd: Add support for eDP PLL configurationBalasubramani Vivekanandan1-1/+146
2024-05-03drm/i915/xe2hpd: Add new C20 PHY SRAM addressBalasubramani Vivekanandan2-32/+81
2024-05-03drm/i915/xe2hpd: Properly disable power in port AJosé Roberto de Souza1-3/+14
2024-05-03drm/i915/bmg: Extend DG2 tc check to futureRadhakrishna Sripada1-4/+3
2024-05-03drm/i915/xe2hpd: Initial cdclk tableClint Taylor1-0/+11
2024-05-03drm/i915/bmg: Define IS_BATTLEMAGE macroBalasubramani Vivekanandan1-1/+9
2024-05-03drm/i915/bmg: Lane reversal requires writes to both context lanesClint Taylor1-5/+5
2024-05-03Merge drm/drm-next into drm-intel-nextRodrigo Vivi1081-8874/+43743
2024-05-03drm/amdgpu: remove ip dump reg_count variableSunil Khatri2-3/+0
2024-05-03drm/amd/display: Fix uninitialized variables in dcn401 and dml21Alex Hung4-8/+10
2024-05-03drm/amd/display: Assign disp_cfg_index_max when dml21Alex Hung1-0/+1
2024-05-03drm/xe/debugfs: Get a runtime_pm reference when setting wedged modeFrancois Dugast1-0/+2
2024-05-03drm/i915/display: Calculate crtc clock rate based on PLL parametersMika Kahola1-1/+2
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