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path: root/drivers/gpu
AgeCommit message (Expand)AuthorFilesLines
2023-11-08drm/i915/dp_mst: Enable DSC passthroughImre Deak1-2/+20
2023-11-08drm/i915/dp: Enable DSC via the connector decompression AUXImre Deak4-21/+101
2023-11-08drm/i915/dp_mst: Enable decompression in the sink from the MST encoder hooksImre Deak2-5/+22
2023-11-08drm/i915/dp_mst: Handle the Synaptics HBlank expansion quirkImre Deak2-4/+131
2023-11-08drm/i915/dp: Disable FEC ready flag in the sinkImre Deak1-8/+13
2023-11-08drm/i915/dp: Wait for FEC detected status in the sinkImre Deak3-0/+80
2023-11-08drm/i915/dp: Rename intel_ddi_disable_fec_state() to intel_ddi_disable_fec()Imre Deak1-5/+4
2023-11-08drm/i915/dp_mst: Add missing DSC compression disablingImre Deak1-0/+2
2023-11-08drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabledImre Deak2-4/+6
2023-11-08drm/i915/dp_mst: Program the DSC PPS SDP for each streamImre Deak2-5/+8
2023-11-08drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platformsImre Deak1-6/+10
2023-11-08drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocationImre Deak1-25/+99
2023-11-08drm/i915/dp: Pass actual BW overhead to m_n calculationImre Deak6-18/+71
2023-11-08drm/i915/dp: Specify the FEC overhead as an increment vs. a remainderImre Deak1-4/+4
2023-11-08drm/i915/dp_mst: Enable FEC early once it's known DSC is neededImre Deak3-3/+15
2023-11-08drm/dp: Add helpers to calculate the link BW overheadImre Deak2-6/+149
2023-11-08drm/dp_mst: Add HBLANK expansion quirk for Synaptics MST hubsImre Deak1-0/+2
2023-11-08drm/dp_mst: Allow DSC in any Synaptics last branch deviceImre Deak1-8/+13
2023-11-08drm/dp_mst: Swap the order of checking root vs. non-root port BW limitationsImre Deak1-5/+8
2023-11-08drm/dp_mst: Factor out a helper to check the atomic state of a topology managerImre Deak1-19/+74
2023-11-08drm/dp_mst: Add helper to determine if an MST port is downstream of another portImre Deak1-0/+52
2023-11-08drm/dp_mst: Fix fractional DSC bpp handlingVille Syrjälä6-25/+13
2023-11-08drm/i915/dp_mst: Fix race between connector registration and setupImre Deak1-8/+8
2023-11-07drm/i915: move display spinlock init to display codeJani Nikula2-2/+1
2023-11-07drm/i915: move display mutex inits to display codeJani Nikula2-6/+6
2023-11-07drm/i915/display: Support PSR entry VSC packet to be transmitted one frame ea...Mika Kahola3-14/+70
2023-11-06drm/i915/dp_mst: Disable DSC on ICL MST outputsImre Deak1-0/+16
2023-11-06drm/i915/tc: Fix -Wformat-truncation in intel_tc_port_initNirmoy Das1-3/+8
2023-11-06drm/i915: Move for_each_engine* out of i915_drv.hTvrtko Ursulin5-15/+18
2023-11-06drm/i915: Remove unused for_each_uabi_class_engineTvrtko Ursulin1-5/+0
2023-11-06drm/i915/dsi: Extract port_ctrl_reg()Ville Syrjälä1-7/+10
2023-11-06drm/i915/dsi: Remove dead GLK checksVille Syrjälä1-2/+2
2023-11-06drm/i915: Extract mchbar_reg()Ville Syrjälä1-13/+14
2023-11-06drm/i915: Stop using a 'reg' variableVille Syrjälä1-9/+6
2023-11-06drm/i915: Extract hsw_chicken_trans_reg()Ville Syrjälä5-25/+23
2023-11-06drm/i915/display: Use intel_bo_to_drm_bo instead of obj->baseJouni Högander1-1/+1
2023-11-04drm/i915: Bump GLK CDCLK frequency when driving multiple pipesVille Syrjälä1-0/+12
2023-11-02drm/i915/display: Use dma_fence interfaces instead of i915_sw_fenceJouni Högander4-95/+61
2023-11-01drm/i915/mst: Always write CHICKEN_TRANSVille Syrjälä1-6/+8
2023-11-01drm/i915/mst: Clear ACT just before triggering payload allocationVille Syrjälä1-2/+2
2023-11-01drm/i915/mst: Disable transcoder before deleting the payloadVille Syrjälä1-6/+2
2023-11-01drm/i915/mst: Swap TRANSCONF vs. FECSTALL_DIS_DPTSTREAM_DPTTG disableVille Syrjälä1-1/+2
2023-10-31drm/i915/mtl: Apply notify_guc to all GTsNirmoy Das1-3/+6
2023-10-31drm/i915/hdcp: Add more conditions to enable hdcpSuraj Kandpal1-2/+12
2023-10-31drm/i915/hdcp: Convert intel_hdcp_enable to a blanket functionSuraj Kandpal4-17/+22
2023-10-31drm/i915/hdcp: Rename HCDP 1.4 enablement functionSuraj Kandpal1-3/+3
2023-10-31drm/i915: Move the g45 PEG band gap HPD workaround to the HPD codeVille Syrjälä3-20/+16
2023-10-31drm/i915: Extract _intel_{enable,disable}_shared_dpll()Ville Syrjälä1-14/+23
2023-10-31drm/i915: Move the DPLL extra power domain handling up one levelVille Syrjälä1-6/+10
2023-10-31drm/i915: Abstract the extra JSL/EHL DPLL4 power domain betterVille Syrjälä2-22/+14
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