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path: root/drivers/gpu/drm
AgeCommit message (Expand)AuthorFilesLines
2010-09-22drm/i915/crt: Use a DDC probe on 0xA0 before load-detectChris Wilson1-4/+35
2010-09-22drm/i915: Disable "disabled FBC" message when a no-opChris Wilson1-0/+3
2010-09-22drm/i915: Drop ring->lazy_requestChris Wilson2-36/+6
2010-09-22drm/i915: Don't offset the pin used for crt_ddcChris Wilson1-1/+1
2010-09-22drm/i915: Clear the gpu_write_list on resetting write_domain upon hangChris Wilson3-28/+42
2010-09-21drm/i915: Don't overwrite the returned error-codeChris Wilson1-3/+3
2010-09-21drm/i915/lvds: Unlock the PP register when panel-fittingChris Wilson1-2/+6
2010-09-21drm/i915: Use the correct DPB GMBUS port for GPIOEChris Wilson1-2/+2
2010-09-21drm/i915: Drop crtc->fb pin on disable.Chris Wilson1-0/+15
2010-09-21drm/i915: Disable output polling across suspend & resumeChris Wilson2-3/+10
2010-09-21intel-gtt: clean up gtt size reportingDaniel Vetter1-1/+0
2010-09-21drm/i915: Track pinned objectsChris Wilson3-14/+26
2010-09-21drm/i915: Drain any pending flips on the fb prior to unpinningChris Wilson3-20/+26
2010-09-21drm/i915: Merge ring flushing and lazy requestsChris Wilson3-32/+24
2010-09-21drm/i915: Track gpu fence usageChris Wilson2-2/+10
2010-09-21drm/i915/ringbuffer: whitespace cleanupChris Wilson2-65/+68
2010-09-21drm/i915: drop alignment ringbuffer parameterDaniel Vetter2-5/+1
2010-09-21drm/i915: don't explicitly initialize ringbuffer members to zeroDaniel Vetter1-33/+0
2010-09-21drm/i915: use new macros to access the ring ctl registerDaniel Vetter2-17/+7
2010-09-21drm/i915: use new macros to access the ring head registerDaniel Vetter2-40/+13
2010-09-21drm/i915: use new macros to access the ring start registerDaniel Vetter2-8/+6
2010-09-21drm/i915: use new macros to access the ring tail registerDaniel Vetter2-50/+22
2010-09-21drm/i915: add relative ring register macrosDaniel Vetter3-0/+12
2010-09-21drm/i915: kill duplicated/unneeded register definesDaniel Vetter1-18/+0
2010-09-21drm/i915: Use ring->flush() instead of MI_FLUSHChris Wilson3-17/+20
2010-09-21drm/i915/ringbuffer: Mark the initialisation structs as constant.Chris Wilson1-3/+3
2010-09-21drm/i915: add a new BSD ring buffer for SandybridgeXiang, Haihao4-8/+159
2010-09-21drm/i915/ringbuffer: Implement advance using set_tailChris Wilson2-17/+1
2010-09-21drm/i915: add set_tail hook in struct intel_ring_bufferXiang, Haihao2-5/+19
2010-09-21drm/i915: do not export the instances of struct intel_ring_bufferXiang, Haihao3-16/+31
2010-09-21drm/i915: fix HAS_BSD with a device info flagXiang, Haihao2-1/+6
2010-09-21drm/i915: Clean up bo lists on all hung gpusChris Wilson3-19/+16
2010-09-21drm/i915: Clear GPU read domains on resetChris Wilson3-0/+19
2010-09-21drm/i915: Clear flushing lists on GPU resetChris Wilson3-0/+23
2010-09-21drm/i915: Only emit a flush request on the active ring.Chris Wilson4-22/+51
2010-09-21drm/i915: Inline i915_gem_ring_retire_request()Chris Wilson1-53/+38
2010-09-21drm/i915/debug: Dump BSD ring buffers to debugfsChris Wilson1-6/+12
2010-09-21drm/i915: After a reset perform a forced modesetChris Wilson1-7/+10
2010-09-21drm/i915: Add support for GPU soft reset on Ironlake.Kenneth Graunke3-7/+27
2010-09-21drm/i915: Rename graphics reset registers.Kenneth Graunke3-8/+10
2010-09-21drm/i915: Actually set the reset bit in i965_reset.Kenneth Graunke1-16/+15
2010-09-21drm/i915: INTEL_INFO->gen supercedes i8xx, i9xx, i965gChris Wilson17-201/+197
2010-09-21drm/i915: Cache LVDS EDIDChris Wilson1-11/+8
2010-09-21Merge branch 'drm-intel-fixes' into HEADChris Wilson39-268/+507
2010-09-21Merge remote branch 'linus' into drm-intel-fixesChris Wilson23-66/+188
2010-09-20drm/i915: Hold a reference to the object whilst unbinding the eviction listChris Wilson1-2/+7
2010-09-18drm/i915: use GMBUS to manage i2c linksChris Wilson21-419/+441
2010-09-17drm/i915,agp/intel: Add second set of PCI-IDs for B43Chris Wilson1-0/+1
2010-09-17drm/i915: Fix Sandybridge fence registersChris Wilson2-22/+51
2010-09-17drm/i915/crt: Downgrade warnings for hotplug failuresChris Wilson1-2/+2
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