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path: root/drivers/gpu/drm/xe/regs
AgeCommit message (Expand)AuthorFilesLines
2023-12-21drm/xe/gsc: GSC FW loadDaniele Ceraolo Spurio1-0/+29
2023-12-21drm/xe/xe2: Add workaround 14020013138Tejas Upadhyay1-0/+3
2023-12-21drm/xe/dg2: Drop Wa_22014600077Matt Roper1-1/+0
2023-12-21drm/xe/xe2: Add workaround 14019449301Tejas Upadhyay1-0/+3
2023-12-21drm/xe/display: Implement display supportMaarten Lankhorst2-14/+1
2023-12-21drm/xe: Raise GT frequency before GuC/HuC loadVinay Belgaumkar1-0/+5
2023-12-21drm/xe/gsc: enable pvc supportAlexander Usyskin1-0/+1
2023-12-21drm/xe/xelpmp: Add Wa_16021867713Gustavo Sousa1-0/+3
2023-12-21drm/xe: implement driver initiated function-resetAndrzej Hajda1-0/+7
2023-12-21drm/xe: Add Wa_14019821291Matt Roper1-0/+2
2023-12-21drm/xe/hwmon: Expose power1_max_intervalBadal Nilawar1-0/+8
2023-12-21drm/xe/xelpmp: Extend Wa_22016670082 to Xe_LPM+Shekhar Chauhan1-0/+1
2023-12-21drm/xe/mocs: MOCS registers are multicast on Xe_HP and beyondMatt Roper1-2/+4
2023-12-21drm/xe: Add performance tuning settings for MTL and Xe2Shekhar Chauhan1-0/+2
2023-12-21drm/xe/xe2: Add initial workaroundsDnyaneshwar Bhadane1-0/+24
2023-12-21drm/xe: Extract MI_* instructions to their own headerMatt Roper1-41/+0
2023-12-21drm/xe: Clarify number of dwords/qwords stored by MI_STORE_DATA_IMMMatt Roper1-0/+3
2023-12-21drm/xe: Separate number of registers from MI_LRI opcodeMatt Roper1-1/+3
2023-12-21drm/xe: Make MI_FLUSH_DW immediate size more explicitMatt Roper1-1/+4
2023-12-21drm/xe/gsc: add HECI2 register offsetsVitaly Lubart1-0/+4
2023-12-21drm/xe: add 28-bit address support in struct xe_regKoby Elbaz1-1/+15
2023-12-21drm/xe: add gt tuning for indirect stateMatt Atwood1-0/+1
2023-12-21drm/xe: Remove devcoredump readout of IPEIRJosé Roberto de Souza1-2/+0
2023-12-21drm/xe: Fix devcoredump readout of IPEHRJosé Roberto de Souza1-1/+0
2023-12-21drm/xe/hwmon: Expose hwmon energy attributeBadal Nilawar2-0/+5
2023-12-21drm/xe/hwmon: Expose input voltage attributeBadal Nilawar1-0/+3
2023-12-21drm/xe/hwmon: Expose power attributesBadal Nilawar2-0/+37
2023-12-21drm/xe/xe2: Update MOCS fields in blitter instructionsHaridhar Kalvala1-0/+4
2023-12-21drm/xe/xe2: Set tile y type in XY_FAST_COPY_BLT to Tile4Haridhar Kalvala1-0/+2
2023-12-21drm/xe: Rename MEM_SET instructionHaridhar Kalvala1-3/+3
2023-12-21drm/xe: Adjust mocs field mask definitionsHaridhar Kalvala1-2/+2
2023-12-21drm/xe/xe2: Extend reserved stolen sizesLucas De Marchi1-1/+1
2023-12-21drm/xe: Add Wa_18028616096Shekhar Chauhan1-0/+1
2023-12-21drm/xe/wa: Apply tile workarounds at probe/resumeMatt Roper1-0/+3
2023-12-21drm/xe/pmu: Enable PMU interfaceAravind Iddamsetty1-0/+5
2023-12-21drm/xe/pvc: Force even num engines to use 64BNiranjana Vishwanathapura1-0/+1
2023-12-21drm/xe/pvc: Blacklist BCS_SWCTRL registerNiranjana Vishwanathapura1-0/+2
2023-12-21drm/xe/xe2: Program GuC's MOCS on Xe2 and beyondMatt Roper1-1/+1
2023-12-21drm/xe/xe2: Handle fused-off CCS enginesMatt Roper1-0/+1
2023-12-21drm/xe/xe2: Add MCR register steering for primary GTMatt Roper1-0/+1
2023-12-21drm/xe/xe2: Add GT topology readoutMatt Roper1-0/+3
2023-12-21drm/xe: enable idle msg and set hysteresis for GSCCSDaniele Ceraolo Spurio1-0/+4
2023-12-21drm/xe: GSC forcewake supportDaniele Ceraolo Spurio1-0/+2
2023-12-21drm/xe: add GSCCS irq supportDaniele Ceraolo Spurio1-0/+2
2023-12-21drm/xe: base definitions for the GSCCSDaniele Ceraolo Spurio2-0/+2
2023-12-21drm/xe/dg2: Remove Wa_15010599737Shekhar Chauhan1-3/+0
2023-12-21drm/xe: Add Wa_14015150844 for DG2 and Xe_LPGMatt Roper1-0/+1
2023-12-21drm/xe: Sort xe_regs.hLucas De Marchi1-30/+33
2023-12-21drm/xe: Carve out top of DSM as reservedLucas De Marchi1-0/+3
2023-12-21drm/xe/mtl: Add support to get C6 residency/status of MTLBadal Nilawar1-2/+9
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