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path: root/drivers/gpu/drm/nouveau/include/nvkm/engine
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2024-07-27drm/nouveau/nvkm: remove perfmonBen Skeggs1-29/+0
This has never really been used for anything, in part due to never having reclocking stable enough in general to attempt to implement dynamic clock changes based on load, etc. To avoid having to rework its interfaces, remove it entirely. Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Danilo Krummrich <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-31drm/nouveau/ofa/r535: initial supportBen Skeggs1-0/+9
Adds support for allocating OFA classes from RM. Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-31drm/nouveau/nvjpg/r535: initial supportBen Skeggs1-0/+8
Adds support for allocating NVJPG classes from RM. Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-31drm/nouveau/nvenc/r535: initial supportBen Skeggs1-0/+2
Adds support for allocating VIDEO_ENCODER classes from RM. Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-31drm/nouveau/nvdec/r535: initial supportBen Skeggs1-0/+2
Adds support for allocating VIDEO_DECODER classes from RM. Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-31drm/nouveau/gr/r535: initial supportBen Skeggs2-0/+2
Adds support for allocating GR classes from RM. Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-31drm/nouveau/ce/r535: initial supportBen Skeggs1-0/+2
Adds support for allocating DMA_COPY classes from RM. Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-31drm/nouveau/fifo/r535: initial supportBen Skeggs1-0/+13
- Adds support for allocating CHANNEL_GPFIFO classes from RM. Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-31drm/nouveau/disp/r535: initial supportBen Skeggs1-0/+19
Adds support for modesetting on RM. Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-31drm/nouveau/gsp/r535: add interrupt handlingBen Skeggs1-0/+2
Fetches the interrupt table from RM, and hooks up the GSP interrupt handler to message queue processing to catch async messages. Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-31drm/nouveau/gsp/r535: add support for booting GSP-RMBen Skeggs1-0/+2
This commit adds the initial code needed to boot the GSP-RM firmware provided by NVIDIA, bringing with it the beginnings of Ada support. Until it's had more testing and time to bake, support is disabled by default (except on Ada). GSP-RM usage can be enabled by passing the "config=NvGspRm=1" module option. Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-31drm/nouveau/nvenc/tu102-: prepare for GSP-RMBen Skeggs1-0/+1
- (temporarily) disable if GSP-RM detected, will be added later - provide empty class list for non-GSP paths - split tu102 from gm107, it will provide host classes later Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-31drm/nouveau/nvdec/tu102-: prepare for GSP-RMBen Skeggs1-0/+1
- (temporarily) disable if GSP-RM detected, will be added later - provide empty class list for non-GSP paths - split tu102- from gm107, they will provide host classes later - fixup HW engine instance masks Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-31drm/nouveau/fifo/tu102-: prepare for GSP-RMBen Skeggs1-0/+3
- (temporarily) disable if GSP-RM detected, will be added later - add dtor() so GSP-RM paths can cleanup properly - add alternate engine context mapping interface for RM engines - add alternate chid interfaces to handle RM USERD oddities Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-07-06drm/nouveau/fifo: remove left-over references to nvkm_fifo_chanBen Skeggs1-1/+1
This was renamed to nvkm_chan in the host rework. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Signed-off-by: Karol Herbst <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-11-09drm/nouveau/gr/ga102: initial supportBen Skeggs1-0/+1
v2: - whitespace Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Gourav Samaiya <[email protected]>
2022-11-09drm/nouveau/acr/ga102: initial supportBen Skeggs2-0/+2
v2. fixup for ga103 early merge Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Gourav Samaiya <[email protected]>
2022-11-09drm/nouveau/fb/ga102: load and boot VPR scrubber FWBen Skeggs2-0/+7
v2. fixup for ga103 early merge Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Gourav Samaiya <[email protected]>
2022-11-09drm/nouveau/fifo: expose function to read engine ctxsw statusBen Skeggs1-0/+1
Needed to support Ampere differences in gr/gf100-: Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/acr: use common falcon HS FW code for ACR FWsBen Skeggs1-19/+13
Adds context binding and support for FWs with a bootloader to the code that was added to load VPR scrubber HS binaries, and ports ACR over to using all of it. - gv100 split from gp108 to handle FW exit status differences Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/flcn: new code to load+boot simple HS FWs (VPR scrubber)Ben Skeggs1-1/+4
Adds the start of common interfaces to load and boot the HS binaries provided by NVIDIA that enable the usage of GR. ACR already handles most of this, but it's very much tied into ACR's init process, and there's other code that could benefit from reusing a lot of this stuff too (ie. VBIOS DEVINIT/PreOS, VPR scrubber). The VPR scrubber code is fairly independent, and a good first target. - adds better debug output to fw loading process, to ease bring-up/debug v2: - whitespace, 0->false Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/flcn: rework falcon resetBen Skeggs1-6/+6
Mostly preparation to fit in Ampere changes, but should result in reset sequences a lot closer to RM's, and perhaps help out with the issues we sometimes see reported in this area. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/sec2: unload RTOS before tearing down WPRBen Skeggs1-1/+3
Reset regs won't be available on Ampere while SEC2 RTOS is running, and we're apparently supposed to be doing this on earlier GPUs too. v2: - fixed some excessive indentation Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/pmu/gm20b,gp10b: boot RTOS from PMU initBen Skeggs1-4/+4
Cleanup before falcon changes. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/fifo/ga100-: initial supportBen Skeggs1-0/+2
- replaces the hacked-up version that existed solely to support TTM v2. remove earlier hack preventing use of non-stall intr for fences Signed-off-by: Ben Skeggs <[email protected]>
2022-11-09drm/nouveau/ce/ga100-: initial supportBen Skeggs1-0/+2
- replaces the hacked-up version that existed solely to support TTM - noop until the next commit, adding proper support for ampere host v2. fixup for ga103 early merge Signed-off-by: Ben Skeggs <[email protected]>
2022-11-09drm/nouveau/fifo: add new channel classesBen Skeggs1-5/+2
Exposes a bunch of the new features that became possible as a result of the earlier commits. DRM will build on this in the future to add support for features such as SCG ("async compute") and multi-device rendering, as part of the work necessary to be able to write a half- decent vulkan driver - finally. For the moment, this just crudely ports DRM to the API changes. - channel class interfaces now the same for all HW classes - channel group class exposed (SCG) - channel runqueue selector exposed (SCG) - channel sub-device id control exposed (multi-device rendering) - channel names in logging will reflect creating process, not fd owner - explicit USERD allocation required by VOLTA_CHANNEL_GPFIFO_A and newer - drm is smarter about determining the appropriate channel class to use Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/fifo: add new engine context handlingBen Skeggs1-9/+0
Builds on the context tracking that was added earlier. - marks engine context PTEs as 'priv' where possible Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/fifo: add RAMFC info to nvkm_chan_funcBen Skeggs1-0/+7
- adds support for specifying SUBDEVICE_ID for channel - rounds non-power-of-two GPFIFO sizes down, rather than up Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/fifo: add USERD info to nvkm_chan_funcBen Skeggs1-2/+10
And use it to cleanup multiple implementations of almost the same thing. - prepares for non-polled / client-provided USERD - only zeroes relevant "registers", rather than entire USERD Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/fifo: add RAMIN info to nvkm_chan_funcBen Skeggs1-2/+2
Currently provided by {chan,dma,gpfifo}*.c, and those are going away. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/fifo: add common runlist controlBen Skeggs1-1/+1
- less dependence on waiting for runlist updates, on GPUs that allow it - supports runqueue selector in RAMRL entries - completes switch to common runl/cgrp/chan topology info Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/fifo: add chan start()/stop()Ben Skeggs1-3/+4
- nvkm_chan_error() built on top, stops channel and sends 'killed' event - removes an odd double-bashing of channel enable regs on kepler and up - pokes doorbell on turing and up, after enabling channel Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/fifo: add runlist wait()Ben Skeggs1-0/+4
- adds g8x/turing registers, which were missing before - switches fermi to polled wait, like later hw (see: 4f2fc25c0f8bc...) Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/fifo: add new engine context trackingBen Skeggs1-1/+2
Channel groups have somewhat more complicated requirements than what we currently support. An engine context is shared between all channels in a channel group, VEID/subctx support (later) brings per-VEID components, and we need to track an individual channel's engine context pointers. This commit adds the structures and refcounting to support the above, wrapping the prior implementation for the moment. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/fifo: add new channel lookup interfacesBen Skeggs2-8/+5
- supports per-runlist CHIDs - channel group lock held across reference, rather than global lock v2: - remove unnecessary parenthesis Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/fifo: tidy up non-stall intr handlingBen Skeggs1-2/+5
- removes a layer of indirection in the intr handling - prevents non-stall ctrl racing with unknown intrs Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/fifo: use runlist engine info to lookup engine classesBen Skeggs1-1/+0
Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/fifo: add cgrp, have all channels be part of oneBen Skeggs1-3/+4
Engine context tracking will move to nvkm_cgrp in later commits, so we create SW-only channel groups on HW without support for them. - switches to nvkm_chid for TSG/channel ID allocation Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/fifo: add common runlist/engine topologyBen Skeggs1-0/+2
Creates an nvkm_runl for each runlist on the GPU, and an nvkm_engn for each engine that is reachable from a runlist. - basically what gk104- already does, but extended to all chips - adds per-runlist CHID allocators (Ampere) - splits g98/gt2xx out from g84 (different target engines) Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/fifo: add runqBen Skeggs1-0/+2
Creates an nvkm_runq for each PBDMA, these will be associated with the relevant runlist(s) later. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/fifo: add chid allocatorBen Skeggs1-0/+3
We need to be able to allocate TSG IDs as well as channel IDs, also, Ampere has per-runlist channel IDs. - holds per-ID private data, which will be used for/to protect lookup - holds an nvkm_event which will be used for events tied to IDs - not used yet beyond setup, and switching use of "fifo->nr - 1" for channel ID mask to "chid->mask" Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/fifo: unify handling of channel classesBen Skeggs1-2/+3
Adds the basic skeleton for common channel (group) interfaces. - common behaviour between <gk104 and >=gk104 impl's - separates priv/user channel objects - passthrough to existing object for now, kludges removed later Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/fifo: add chid_nr()Ben Skeggs1-2/+0
- reads channel count from GPU from gm200 onwards - removes gm20b/gp10b (they become identical to gm200/gp100) Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/fifo: expose channel killed in host channel event classBen Skeggs1-0/+1
Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/fifo: expose non-stall intr in host channel event classBen Skeggs1-0/+1
Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/disp: switch vblank semaphore release to nvkm_event_ntfyBen Skeggs1-0/+1
Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-07drm/nouveau/disp: move LVDS protocol information into acquireBen Skeggs1-7/+1
Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-07-27drm/nouveau/disp: add supervisor mutexBen Skeggs1-0/+1
Will be used to protect NVIF_CLASS_OUTP method calls from racing with in-progress supervisor handling. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2022-07-27drm/nouveau/disp: add common channel class handlingBen Skeggs1-0/+1
Replaces a bunch of unnecessarily duplicated boilerplate in per-chipset code with a simpler, common, implementation. Channel "awaken" notify code is completely gone for now. KMS has never made use of it so far, and event notify handling is about to be changed in general anyway. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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