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2024-10-15drm/msm/a6xx+: Insert a fence wait before SMMU table updateRob Clark1-3/+13
The CP_SMMU_TABLE_UPDATE _should_ be waiting for idle, but on some devices (x1-85, possibly others), it seems to pass that barrier while there are still things in the event completion FIFO waiting to be written back to memory. Work around that by adding a fence wait before context switch. The CP_EVENT_WRITE that writes the fence is the last write from a submit, so seeing this value hit memory is a reliable indication that it is safe to proceed with the context switch. v2: Only emit CP_WAIT_TIMESTAMP on a7xx, as it is not supported on a6xx. Conversely, I've not been able to reproduce this issue on a6xx, so hopefully it is limited to a7xx, or perhaps just certain a7xx devices. Fixes: af66706accdf ("drm/msm/a6xx: Add skeleton A7xx support") Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/63 Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Akhil P Oommen <[email protected]> Signed-off-by: Abhinav Kumar <[email protected]>
2024-09-01drm/msm/adreno: Add A306A supportOtto Pflüger3-3/+28
Add support for Adreno 306A GPU what is found in MSM8917 SoC. This GPU marketing name is Adreno 308. Signed-off-by: Otto Pflüger <[email protected]> [use internal name of the GPU, reword the commit message] Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Barnabás Czémán <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/605403/ Signed-off-by: Rob Clark <[email protected]>
2024-09-01drm/msm/a6xx: Add A621 supportKonrad Dybcio4-1/+106
A621 is a clear A662 derivative (same lineage as A650), no explosions or sick features, other than a NoC bug which can stall the GPU.. Add support for it. Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/611100/ Signed-off-by: Rob Clark <[email protected]>
2024-09-01drm/msm/a6xx: Set GMU CGC properties on a6xx tooKonrad Dybcio3-10/+17
This was apparently never done before.. Program the expected values. This also gets rid of sneakily setting that register through the HWCG reg list on A690. Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/611098/ Signed-off-by: Rob Clark <[email protected]>
2024-09-01drm/msm/a6xx: Use the per-GPU value for gmu_cgc_modeKonrad Dybcio1-4/+2
This register's magic value differs wildly between different GPUs, use the hardcoded data instead of trying to make some logic out of it. Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/611096/ Signed-off-by: Rob Clark <[email protected]>
2024-09-01drm/msm/a6xx: Store correct gmu_cgc_mode in struct a6xx_infoKonrad Dybcio2-0/+20
Store the correct values that we happen to have for some A7xx SKUs in the GPU info struct and fill out the missing information for A6xx GPUs based on downstream kernel information. Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/611094/ [add missing entry to a615 catalog to resolve conflict] Signed-off-by: Rob Clark <[email protected]>
2024-09-01drm/msm/a6xx: Store primFifoThreshold in struct a6xx_infoKonrad Dybcio3-19/+21
The if-else monster is so unmaintainable that one case is repeated twice. Get rid of it. Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/611092/ [add missing entry to a615 catalog to resolve conflict] Signed-off-by: Rob Clark <[email protected]>
2024-09-01drm/msm/a6xx: Evaluate adreno_is_a650_family in pdc_in_aop checkKonrad Dybcio1-2/+1
A650 family includes A660 family (they've got a big family), A650 itself, and some more A6XX_GEN3 SKUs, all of which should fall into the same branch of the if-condition. Simplify that. Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/605206/ Signed-off-by: Rob Clark <[email protected]>
2024-09-01drm/msm/a5xx: workaround early ring-buffer emptiness checkVladimir Lypak3-0/+9
There is another cause for soft lock-up of GPU in empty ring-buffer: race between GPU executing last commands and CPU checking ring for emptiness. On GPU side IRQ for retire is triggered by CACHE_FLUSH_TS event and RPTR shadow (which is used to check ring emptiness) is updated a bit later from CP_CONTEXT_SWITCH_YIELD. Thus if GPU is executing its last commands slow enough or we check that ring too fast we will miss a chance to trigger switch to lower priority ring because current ring isn't empty just yet. This can escalate to lock-up situation described in previous patch. To work-around this issue we keep track of last submit sequence number for each ring and compare it with one written to memptrs from GPU during execution of CACHE_FLUSH_TS event. Fixes: b1fc2839d2f9 ("drm/msm: Implement preemption for A5XX targets") Signed-off-by: Vladimir Lypak <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/612047/ Signed-off-by: Rob Clark <[email protected]>
2024-09-01drm/msm/a5xx: fix races in preemption evaluation stageVladimir Lypak2-2/+23
On A5XX GPUs when preemption is used it's invietable to enter a soft lock-up state in which GPU is stuck at empty ring-buffer doing nothing. This appears as full UI lockup and not detected as GPU hang (because it's not). This happens due to not triggering preemption when it was needed. Sometimes this state can be recovered by some new submit but generally it won't happen because applications are waiting for old submits to retire. One of the reasons why this happens is a race between a5xx_submit and a5xx_preempt_trigger called from IRQ during submit retire. Former thread updates ring->cur of previously empty and not current ring right after latter checks it for emptiness. Then both threads can just exit because for first one preempt_state wasn't NONE yet and for second one all rings appeared to be empty. To prevent such situations from happening we need to establish guarantee for preempt_trigger to make decision after each submit or retire. To implement this we serialize preemption initiation using spinlock. If switch is already in progress we need to re-trigger preemption when it finishes. Fixes: b1fc2839d2f9 ("drm/msm: Implement preemption for A5XX targets") Signed-off-by: Vladimir Lypak <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/612045/ Signed-off-by: Rob Clark <[email protected]>
2024-09-01drm/msm/a5xx: properly clear preemption records on resumeVladimir Lypak1-0/+2
Two fields of preempt_record which are used by CP aren't reset on resume: "data" and "info". This is the reason behind faults which happen when we try to switch to the ring that was active last before suspend. In addition those faults can't be recovered from because we use suspend and resume to do so (keeping values of those fields again). Fixes: b1fc2839d2f9 ("drm/msm: Implement preemption for A5XX targets") Signed-off-by: Vladimir Lypak <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/612043/ Signed-off-by: Rob Clark <[email protected]>
2024-09-01drm/msm/a5xx: disable preemption in submits by defaultVladimir Lypak1-2/+6
Fine grain preemption (switching from/to points within submits) requires extra handling in command stream of those submits, especially when rendering with tiling (using GMEM). However this handling is missing at this point in mesa (and always was). For this reason we get random GPU faults and hangs if more than one priority level is used because local preemption is enabled prior to executing command stream from submit. With that said it was ahead of time to enable local preemption by default considering the fact that even on downstream kernel it is only enabled if requested via UAPI. Fixes: a7a4c19c36de ("drm/msm/a5xx: fix setting of the CP_PREEMPT_ENABLE_LOCAL register") Signed-off-by: Vladimir Lypak <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/612041/ Signed-off-by: Rob Clark <[email protected]>
2024-09-01drm/msm/adreno: Assign msm_gpu->pdev earlier to avoid nullptrsKonrad Dybcio1-0/+1
There are some cases, such as the one uncovered by Commit 46d4efcccc68 ("drm/msm/a6xx: Avoid a nullptr dereference when speedbin setting fails") where msm_gpu_cleanup() : platform_set_drvdata(gpu->pdev, NULL); is called on gpu->pdev == NULL, as the GPU device has not been fully initialized yet. Turns out that there's more than just the aforementioned path that causes this to happen (e.g. the case when there's speedbin data in the catalog, but opp-supported-hw is missing in DT). Assigning msm_gpu->pdev earlier seems like the least painful solution to this, therefore do so. Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/602742/ Signed-off-by: Rob Clark <[email protected]>
2024-08-30drm/msm: Fix incorrect file name output in adreno_request_fw()Aleksandr Mishin1-1/+1
In adreno_request_fw() when debugging information is printed to the log after firmware load, an incorrect filename is printed. 'newname' is used instead of 'fwname', so prefix "qcom/" is being added to filename. Looks like "copy-paste" mistake. Fix this mistake by replacing 'newname' with 'fwname'. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 2c41ef1b6f7d ("drm/msm/adreno: deal with linux-firmware fw paths") Signed-off-by: Aleksandr Mishin <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/602382/ Signed-off-by: Rob Clark <[email protected]>
2024-08-30drm/msm: Fix UBWC macrotile_mode for a680Connor Abbott1-0/+3
Make it match the MDSS settings for sc8180x and downstream. Note that without the previous commit that exposes the value of macrotile_mode to mesa, this will break mesa which expects the legacy default value of 0. Therefore we do *not* want to backport it. Signed-off-by: Connor Abbott <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/607398/ Signed-off-by: Rob Clark <[email protected]>
2024-08-30drm/msm: Expose expanded UBWC config uapiConnor Abbott1-0/+6
This adds extra parameters that affect UBWC tiling that will be used by the Mesa implementation of VK_EXT_host_image_copy. Signed-off-by: Connor Abbott <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/607401/ Signed-off-by: Rob Clark <[email protected]>
2024-08-30drm/msm: Expand UBWC config settingConnor Abbott3-17/+53
According to downstream we should be setting RBBM_NC_MODE_CNTL to a non-default value on a663 and a680, we don't support a663 and on a680 we're leaving it at the wrong (suboptimal) value. Just set it on all GPUs. Similarly, plumb through level2_swizzling_dis which will be necessary on a663. ubwc_mode is expanded and renamed to ubwc_swizzle to match the name on the display side. Similarly macrotile_mode should match the display side. Signed-off-by: Connor Abbott <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/607397/ Signed-off-by: Rob Clark <[email protected]>
2024-08-30drm/msm: Fix CP_BV_DRAW_STATE_ADDR nameConnor Abbott1-1/+1
This was missed because we weren't using the a750-specific indexed regs. Fixes: f3f8207d8aed ("drm/msm: Add devcoredump support for a750") Signed-off-by: Connor Abbott <[email protected]> Reviewed-by: Akhil P Oommen <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/607394/ Signed-off-by: Rob Clark <[email protected]>
2024-08-30drm/msm: Dump correct dbgahb clusters on a750Connor Abbott1-2/+5
This was missed thanks to the family mixup fixed in the previous commit. Fixes: f3f8207d8aed ("drm/msm: Add devcoredump support for a750") Signed-off-by: Connor Abbott <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/607393/ Signed-off-by: Rob Clark <[email protected]>
2024-08-30drm/msm: Use a7xx family directly in gpu_stateConnor Abbott1-21/+20
With a7xx, we need to import a new header for each new generation and switch to a different list of registers, instead of making backwards-compatible changes. Using the helpers inadvertently made a750 use the a740 list of registers, instead use the family directly to fix this. Fixes: f3f8207d8aed ("drm/msm: Add devcoredump support for a750") Signed-off-by: Connor Abbott <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/607392/ Signed-off-by: Rob Clark <[email protected]>
2024-08-30drm/msm/adreno: add a615 supportRichard Acayan1-0/+27
The Adreno A615 is used in SDM670. Add an entry to support it. Signed-off-by: Richard Acayan <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/607238/ Signed-off-by: Rob Clark <[email protected]>
2024-08-30drm/msm/a6xx: Add A642L speedbin (0x81)Eugene Lepshy1-0/+1
According to downstream, A642L's speedbin is 129 and uses 4 as index Signed-off-by: Eugene Lepshy <[email protected]> Signed-off-by: Danila Tikhonov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/606722/ Signed-off-by: Rob Clark <[email protected]>
2024-08-30drm/msm/adreno: Use kvmemdup to simplify the codeLi Zetao1-4/+2
Use kvmemdup instead of kvmalloc() + memcpy() to simplify the code. No functional change intended. Signed-off-by: Li Zetao <[email protected]> Reviewed-by: Akhil P Oommen <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/609596/ Signed-off-by: Rob Clark <[email protected]>
2024-08-15drm/msm/adreno: Fix error return if missing firmware-nameRob Clark1-1/+1
-ENODEV is used to signify that there is no zap shader for the platform, and the CPU can directly take the GPU out of secure mode. We want to use this return code when there is no zap-shader node. But not when there is, but without a firmware-name property. This case we want to treat as-if the needed fw is not found. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Akhil P Oommen <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/604564/
2024-07-02drm/msm/a6xx: Add missing __always_unusedRob Clark1-1/+1
The __build_asserts() function only exists to have a place to put build-time asserts. Reported-by: kernel test robot <[email protected]> Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/601606/
2024-07-01drm/msm/adreno: Add support for Adreno 505 GPUDaniil Titov3-12/+35
This GPU is found on SoCs such as MSM8937 (450 MHz), MSM8940 (475 MHz), SDM439 (650 MHz). Signed-off-by: Daniil Titov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Barnabás Czémán <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/601411/ Signed-off-by: Rob Clark <[email protected]>
2024-06-29drm/msm/adreno: Introduce gmu_chipid for a740 & a750Akhil P Oommen2-22/+3
To simplify, introduce the new gmu_chipid for a740 & a750 GPUs. Signed-off-by: Akhil P Oommen <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/601396/ Signed-off-by: Rob Clark <[email protected]>
2024-06-29drm/msm/adreno: Add support for X185 GPUAkhil P Oommen5-3/+36
Add support in drm/msm driver for the Adreno X185 gpu found in Snapdragon X1 Elite chipset. Signed-off-by: Akhil P Oommen <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/601399/ Signed-off-by: Rob Clark <[email protected]>
2024-06-29drm/msm/adreno: fix a743 and a740 cx mem initNeil Armstrong1-8/+3
Disable the call to qcom_scm_gpu_init_regs() for a730 and a740 after init failures on the HDK8550 and HDK8450 platforms: msm_dpu ae01000.display-controller: failed to load adreno gpu msm_dpu ae01000.display-controller: failed to bind 3d00000.gpu (ops a3xx_ops [msm]): -5 msm_dpu ae01000.display-controller: adev bind failed: -5 While debugging, it happens the call to: qcom_scm_gpu_init_regs(QCOM_SCM_GPU_ALWAYS_EN_REQ) returns -5 and makes the gpu fail to initialize. Remove the scm call since it's not done downstream either and works fine without. Fixes: 14b27d5df3ea ("drm/msm/a7xx: Initialize a750 "software fuse"") Signed-off-by: Neil Armstrong <[email protected]> Reviewed-by: Connor Abbott <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/600972/ Signed-off-by: Rob Clark <[email protected]>
2024-06-29drm/msm/adreno: fix a7xx gpu initNeil Armstrong1-1/+1
The gpulist has twice the a6xx gpulist, replace the second one with the a7xx gpulist. Solves: msm_dpu ae01000.display-controller: Unknown GPU revision: 7.3.0.1 msm_dpu ae01000.display-controller: Unknown GPU revision: 67.5.10.1 msm_dpu ae01000.display-controller: Unknown GPU revision: 67.5.20.1 on SM8450, SM8550 & SM8560. Fixes: 8ed322f632a9 ("drm/msm/adreno: Split up giant device table") Signed-off-by: Neil Armstrong <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/600939/ Signed-off-by: Rob Clark <[email protected]>
2024-06-29Revert "drm/msm/a6xx: Poll for GBIF unhalt status in hw_init"Konrad Dybcio1-4/+0
Commit f6ebff4fe810 ("drm/msm/adreno: De-spaghettify the use of memory barriers") made some fixups relating to write arrival, ensuring that the GPU's memory interface has *really really really* been told to come out of reset. That in turn rendered the hacky commit being reverted no longer necessary. Get rid of it. This reverts commit b77532803d11 ("drm/msm/a6xx: Poll for GBIF unhalt status in hw_init") Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/600870/ Reviewed-by: Akhil P Oommen <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2024-06-29drm/msm/adreno: De-spaghettify the use of memory barriersKonrad Dybcio2-7/+7
Memory barriers help ensure instruction ordering, NOT time and order of actual write arrival at other observers (e.g. memory-mapped IP). On architectures employing weak memory ordering, the latter can be a giant pain point, and it has been as part of this driver. Moreover, the gpu_/gmu_ accessors already use non-relaxed versions of readl/writel, which include r/w (respectively) barriers. Replace the barriers with a readback (or drop altogether where possible) that ensures the previous writes have exited the write buffer (as the CPU must flush the write to the register it's trying to read back). Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/600869/ Reviewed-by: Akhil P Oommen <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2024-06-21drm/msm/a7xx: Add missing register writes from downstreamConnor Abbott1-0/+11
This isn't known to fix anything yet, but it's a good idea to add it. Signed-off-by: Connor Abbott <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/592043/ Signed-off-by: Rob Clark <[email protected]>
2024-06-21drm/msm: Add MSM_PARAM_RAYTRACING uapiConnor Abbott1-0/+3
Expose the value of the software fuse to userspace. Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Connor Abbott <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/592044/ Signed-off-by: Rob Clark <[email protected]>
2024-06-21drm/msm/a7xx: Initialize a750 "software fuse"Connor Abbott2-1/+92
On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to initialize cx_mem. Copy this from downstream (minus BCL which we currently don't support). On a750, this includes a new "fuse" register which can be used by qcom_scm to fuse off certain features like raytracing in software. The fuse is default off, and is initialized by calling the method. Afterwards we have to read it to find out which features were enabled. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Connor Abbott <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/592042/ Signed-off-by: Rob Clark <[email protected]>
2024-06-21drm/msm/adreno: Check for zap node availabilityRob Clark1-1/+1
This should allow disabling the zap node via an overlay, for slbounce. Suggested-by: Nikita Travkin <[email protected]> Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/594572/
2024-06-21drm/msm: Add obj flags to gpu devcoredumpRob Clark1-0/+1
When debugging faults, it is useful to know how the BO is mapped (cached vs WC, gpu readonly, etc). Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Akhil P Oommen <[email protected]> Acked-by: Konrad Dybcio <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/593854/
2024-06-20drm/msm/a6xx: Fix A702 UBWC modeKonrad Dybcio1-1/+1
UBWC_MODE is a one-bit-wide field, so a value of 2 is obviously bogus. Replace it with the correct value (0). Fixes: 18397519cb62 ("drm/msm/adreno: Add A702 support") Reported-by: Connor Abbott <[email protected]> Closes: https://lore.kernel.org/linux-arm-msm/CACu1E7FTN=kwaDJMNiTmFspALzj2+Q-nvsN5ugi=vz4RdUGvGw@mail.gmail.com/ Signed-off-by: Konrad Dybcio <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/597359/ Signed-off-by: Rob Clark <[email protected]>
2024-06-20drm/msm/a6xx: use __unused__ to fix compiler warnings for gen7_* includesAbhinav Kumar1-8/+5
GCC diagnostic pragma method throws below warnings in some of the versions drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c:16:9: warning: unknown option after '#pragma GCC diagnostic' kind [-Wpragmas] #pragma GCC diagnostic ignored "-Wunused-const-variable" ^ In file included from drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c:18:0: drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h:924:19: warning: 'gen7_0_0_external_core_regs' defined but not used [-Wunused-variable] static const u32 *gen7_0_0_external_core_regs[] = { ^ In file included from drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c:19:0: drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h:748:19: warning: 'gen7_2_0_external_core_regs' defined but not used [-Wunused-variable] static const u32 *gen7_2_0_external_core_regs[] = { ^ In file included from drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c:20:0: drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h:1188:43: warning: 'gen7_9_0_sptp_clusters' defined but not used [-Wunused-variable] static struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] = { ^ drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h:1438:19: warning: 'gen7_9_0_external_core_regs' defined but not used [-Wunused-variable] static const u32 *gen7_9_0_external_core_regs[] = { Remove GCC version dependency by using __unused__ for the unused gen7_* includes. Changes in v2: - Fix the warnings in the commit text - Use __attribute((__unused__)) instead of local assignment changes in v3: - drop the Link from the auto add changes in v4: - replace __attribute((__unused__)) with __always_unused Fixes: 64d6255650d4 ("drm/msm: More fully implement devcoredump for a7xx") Suggested-by: Rob Clark <[email protected]> Signed-off-by: Abhinav Kumar <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/597265/ [Add gen7_9_0_cx_debugbus_blocks as well] Signed-off-by: Rob Clark <[email protected]>
2024-06-20drm/msm/adreno: Move CP_PROTECT settings to hw catalogRob Clark4-251/+268
Move the CP_PROTECT settings into the hw catalog. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/599731/
2024-06-20drm/msm/adreno: Move hwcg table into a6xx specific infoRob Clark4-19/+67
Introduce a6xx_info where we can stash gen specific stuff without polluting the toplevel adreno_info struct. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/599728/
2024-06-20drm/msm/adreno: Move hwcg regs to a6xx hw catalogRob Clark3-620/+619
Move the hwcg tables into the hw catalog. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/599727/
2024-06-20drm/msm/adreno: Split catalog into separate filesRob Clark6-619/+675
Split each gen's gpu table into it's own file. Only code-motion, no functional change. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/599725/
2024-06-20drm/msm/adreno: Split up giant device tableRob Clark2-14/+63
Split into a separate table per generation, in preparation to move each gen's device table to it's own file. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/599723/
2024-05-07drm/msm/a6xx: Cleanup indexed regs const'nessRob Clark2-10/+13
These tables were made non-const in commit 3cba4a2cdff3 ("drm/msm/a6xx: Update ROQ size in coredump") in order to avoid powering up the GPU when reading back a devcoredump. Instead let's just stash the count that is potentially read from hw in struct a6xx_gpu_state_obj, and make the tables const again. Signed-off-by: Rob Clark <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/592699/
2024-05-05drm/msm: Add devcoredump support for a750Connor Abbott1-18/+46
Add an a750 case to the various places where we choose a list of registers. Patchwork: https://patchwork.freedesktop.org/patch/592519/ Signed-off-by: Connor Abbott <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/592519 Signed-off-by: Rob Clark <[email protected]>
2024-05-05drm/msm: Adjust a7xx GBIF debugbus dumpingConnor Abbott2-4/+4
Use the kgsl-style list of indices, because this is about to change for a750 and we want to reuse the downstream header directly. Patchwork: https://patchwork.freedesktop.org/patch/592520/ Signed-off-by: Connor Abbott <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/592520 Signed-off-by: Rob Clark <[email protected]>
2024-05-04drm/msm: Fix imported a750 snapshot header for upstreamConnor Abbott1-434/+454
Add A7XX prefixes necessary because we use the same code for dumping a6xx and a7xx, fix register name prefixes for upstream, and use the upstream header. Patchwork: https://patchwork.freedesktop.org/patch/592517/ Signed-off-by: Connor Abbott <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/592517 Signed-off-by: Rob Clark <[email protected]>
2024-05-04drm/msm: Import a750 snapshot registers from kgslConnor Abbott1-0/+1426
Import from kgsl commit 809ee24fe560. Signed-off-by: Connor Abbott <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/592516/ Signed-off-by: Rob Clark <[email protected]>
2024-05-04drm/msm/a6xx: Avoid a nullptr dereference when speedbin setting failsKonrad Dybcio1-1/+2
Calling a6xx_destroy() before adreno_gpu_init() leads to a null pointer dereference on: msm_gpu_cleanup() : platform_set_drvdata(gpu->pdev, NULL); as gpu->pdev is only assigned in: a6xx_gpu_init() |_ adreno_gpu_init |_ msm_gpu_init() Instead of relying on handwavy null checks down the cleanup chain, explicitly de-allocate the LLC data and free a6xx_gpu instead. Fixes: 76efc2453d0e ("drm/msm/gpu: Fix crash during system suspend after unbind") Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/588919/ Signed-off-by: Rob Clark <[email protected]>
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