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path: root/drivers/gpu/drm/i915
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2013-12-23Merge tag 'drm-intel-next-2013-12-13' of git://people.freedesktop.org/~danvet...Dave Airlie28-506/+947
2013-12-18drm: Kill DRM_COPY_(TO|FROM)_USERDaniel Vetter1-3/+3
2013-12-18drm: Kill DRM_HZDaniel Vetter1-1/+1
2013-12-18drm: kill DRIVER_REQUIRE_AGPDaniel Vetter2-2/+6
2013-12-18drm/dp: Use AUX constants from specificationThierry Reding1-18/+19
2013-12-18Merge tag 'drm-intel-next-2013-11-29' of git://people.freedesktop.org/~danvet...Dave Airlie34-1177/+2044
2013-12-13drm/i915/bdw: Implement ff workaroundsBen Widawsky2-3/+10
2013-12-13drm/i915/bdw: Force all Data Cache Data Port access to be Non-CoherentBen Widawsky2-0/+12
2013-12-13drm/i915/bdw: Don't use forcewake needlesslyVille Syrjälä1-1/+1
2013-12-13drm/i915: Clear out old GT FIFO errors in intel_uncore_early_sanitize()Ville Syrjälä1-0/+5
2013-12-12drm/i915: dont call irq_put when irq test is onMika Kuoppala1-3/+5
2013-12-12drm/i915: Rework the FBC interval/stall stuff a bitVille Syrjälä2-22/+15
2013-12-12drm/i915: Enable FBC for all mobile gen2 and gen3 platformsVille Syrjälä1-0/+3
2013-12-12drm/i915: FBC_CONTROL2 is gen4 onlyVille Syrjälä1-6/+10
2013-12-12drm/i915: Gen2 FBC1 CFB pitch wants 32B unitsVille Syrjälä1-2/+5
2013-12-12drm/i915: split intel_ddi_pll_mode_set in 2 piecesPaulo Zanoni3-20/+94
2013-12-12drm/i915: Fix timeout with missed interrupts in __wait_seqnoMika Kuoppala1-8/+6
2013-12-12drm/i915: touch VGA MSR after we enable the power wellPaulo Zanoni1-0/+15
2013-12-12drm/i915: extract hsw_power_well_post_{enable, disable}Paulo Zanoni1-31/+44
2013-12-12drm/i915: remove i915_disable_vga_mem declarationPaulo Zanoni1-1/+0
2013-12-11drm/i915: Parametrize the dphy and other spec specific parametersShobhit Kumar2-15/+28
2013-12-11drm/i915: Remove redundant DSI PLL enablingShobhit Kumar1-3/+0
2013-12-11drm/i915: Reorganize the DSI enable/disable sequenceShobhit Kumar2-33/+79
2013-12-11drm/i915: Try harder to get best m, n, p values with minimal errorShobhit Kumar1-10/+20
2013-12-11drm/i915: Compute dsi_clk from pixel clockShobhit Kumar1-58/+31
2013-12-11drm/i915: Use FLISDSI interface for band gap resetShobhit Kumar4-39/+25
2013-12-11drm/i915: Add more dev ops for MIPI sub encoderShobhit Kumar2-1/+13
2013-12-11drm/i915: Decrease gen2 vco frequency minimum to 908 MHzVille Syrjälä1-3/+3
2013-12-11drm/i915: Fix 66 MHz LVDS SSC freq for gen2Ville Syrjälä2-11/+10
2013-12-11drm/i915: Increase gen2 vco frequency limit to 1512 MHzVille Syrjälä1-3/+3
2013-12-11drm/i915: Change N divider minimum from 3 to 2 for gen2Ville Syrjälä1-3/+3
2013-12-11drm/i915: Extract p2 divider correctly for gen2 LVDS dual channelVille Syrjälä1-2/+7
2013-12-11drm/i915: Record BB_ADDR for every ringVille Syrjälä3-8/+9
2013-12-11drm/i915: Use 32bit read for BB_ADDRVille Syrjälä1-1/+1
2013-12-11drm/i915: fix VDD override off waitPaulo Zanoni1-1/+3
2013-12-11drm/i915: don't touch the VDD when disabling the panelPaulo Zanoni2-10/+2
2013-12-10drm/i915: don't enable VDD just to enable the panelPaulo Zanoni1-2/+0
2013-12-10drm/i915: add runtime PM support on HaswellPaulo Zanoni1-0/+4
2013-12-10drm/i915: disable interrupts when enabling PC8Paulo Zanoni1-17/+9
2013-12-10drm/i915: do not assert DE_PCH_EVENT_IVB enabledPaulo Zanoni1-1/+1
2013-12-10drm/i915: get a runtime PM reference when the panel VDD is onPaulo Zanoni1-0/+7
2013-12-10drm/i915: add some runtime PM get/put callsPaulo Zanoni5-7/+70
2013-12-10drm/i915: add runtime put/get calls at the basic placesPaulo Zanoni2-6/+27
2013-12-10drm/i915: do adapter power state notification at runtime PMPaulo Zanoni1-0/+2
2013-12-10drm/i915: add initial Runtime PM functionsPaulo Zanoni6-0/+117
2013-12-10drm/i915: get a PC8 reference when enabling the power wellPaulo Zanoni1-2/+13
2013-12-10drm/i915: WARN if !HAS_PC8 when enabling/disabling PC8Paulo Zanoni1-0/+4
2013-12-10drm/i915: Move VLV PHY CRI clock enable into intel_init_dpio()Ville Syrjälä1-7/+4
2013-12-10drm/i915: Don't cast away const from infoframe bufferVille Syrjälä3-12/+12
2013-12-10drm/i915: Make downclock deduction common for all panelsVandana Kannan3-54/+78
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