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2024-06-17drm/i915: move comments about FSB straps to proper placeJani Nikula1-0/+8
Move the comment about FSB straps to where the relevant register is read. Suggested-by: Ville Syrjälä <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/8a5b6cd3db80259c30263861f1a9ff04fea2e7f0.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-06-17drm/i915: use i9xx_fsb_freq() for GT clock frequencyJani Nikula2-1/+2
Reuse i9xx_fsb_freq() for GT clock frequency initialization instead of depending on rawclk_freq. Note: If the init order was changed, we could use i915->fsb_freq directly. However, GT clock initialization is done in i915_driver_mmio_probe(), but intel_dram_detect() later in i915_driver_hw_probe(), with a dependency on intel_pcode_init(). Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/0678d8ec9772725b47d4fa5b14e3b3a34256d5cf.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-06-17drm/i915: extend the fsb_freq initialization to more platformsJani Nikula1-14/+41
Initialize fsb frequency for more platforms to be able to use it for GT clock and rawclk frequency initialization. Note: There's a discrepancy between existing pnv_fsb_freq() and i9xx_hrawclk() regarding CLKCFG interpretation. Presume all PNV is mobile. Default to 1333 MHz for unknown values, similar to i9xx_hrawclk(). v2: - Add MISSING_CASE() (Ville) - Default to the same frequency for both branches (Ville) Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/7cd6dbd4dafb900ac1dd12be0ec096ff1d5fc6cf.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-06-17drm/i915: convert fsb_freq and mem_freq to kHzJani Nikula1-25/+25
We'll want to use fsb frequency for deriving GT clock and rawclk frequencies in the future. Increase the accuracy by converting to kHz. Do the same for mem freq to be aligned. Round the frequencies ending in 666 to 667. v2: Also handle mem_freq in gen5_rps_init() (Ville) Reviewed-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/17fe2544b876549f63fac0f956273f5f282081b3.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-06-17drm/i915/dram: rearrange mem freq initJani Nikula1-34/+25
Follow the same style in mem freq init as in fsb freq init, returning the value instead of assigning in multiple places. Reviewed-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/f098ccdbb0c42016d5dad81e0b089bb4babe29f0.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-06-17drm/i915/dram: split out pnv DDR3 detectionJani Nikula1-4/+8
Split out the PNV DDR3 detection to a distinct step instead of conflating it with mem freq detection. Reviewed-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/c4bf9d32479ab5024e9daa37a996508f543f05e9.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-06-17drm/i915/dram: separate fsb freq detection from mem freqJani Nikula1-46/+60
To simplify further changes, add separate functions for reading the fsb frequency. This ends up reading CLKCFG register twice, but it's not a big deal. Reviewed-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/7582651aa21ac2c1472111c4e81ba8fee182f80e.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-05-31drm: move i915_drm.h under include/drm/intelJani Nikula1-1/+1
Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. v2: Also fix comment in intel_pci_config.h (Ilpo) Cc: Daniel Vetter <[email protected]> Cc: Dave Airlie <[email protected]> Cc: Lucas De Marchi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Hans de Goede <[email protected]> Cc: Ilpo Järvinen <[email protected]> Acked-by: Lucas De Marchi <[email protected]> Acked-by: Rodrigo Vivi <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/0e344a72e9be596ac2b8b55a26fd674a96f03cdc.1717075103.git.jani.nikula@intel.com
2024-05-03drm/i915/bmg: BMG should re-use MTL's south display logicMatt Roper1-2/+2
Battlemage's south display is the same as Meteor Lake's, including the need to invert the HPD pins, which Lunar Lake does not need. Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Dnyaneshwar Bhadane <[email protected]> Signed-off-by: Radhakrishna Sripada <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-05-03drm/i915/xe2hpd: Add max memory bandwidth algorithmMatt Roper1-0/+4
Unlike DG2, Xe2_HPD does support multiple GV points with different maximum memory bandwidths, but uses a much simpler algorithm than igpu platforms use. Bspec: 64631 CC: Jani Nikula <[email protected]> Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Radhakrishna Sripada <[email protected]> Signed-off-by: Radhakrishna Sripada <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-19drm/i915/display: Add meaningful traces for QGV point info error handlingStanislav Lisovskiy1-0/+2
For debug purposes we need those - error path won't flood the log, however there has been already numerous cases, when due to lack of debugs, we couldn't immediately tell what was the problem on customer machine, which slowed down the investigation, requiring to get access to target device and adding those traces manually. v2: - Make the debug more generic and move it to intel_dram_detect (Gustavo Sousa) v3: - Use %u for unsigned variable in debug prints (Gustavo) Reviewed-by: Gustavo Sousa <[email protected]> Signed-off-by: Stanislav Lisovskiy <[email protected]> Signed-off-by: Vinod Govindapillai <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-01-03drm/i915/mtl: Add fake PCH for Meteor LakeHaridhar Kalvala2-13/+9
Correct the implementation trying to detect MTL PCH with the MTL fake PCH id. On MTL, both the North Display (NDE) and South Display (SDE) functionality reside on the same die (the SoC die in this case), unlike many past platforms where the SDE was on a separate PCH die. The code is (badly) structured today in a way that assumes the SDE is always on the PCH for modern platforms, so on platforms where we don't actually need to identify the PCH to figure out how the SDE behaves (i.e., all DG1/2 GPUs as well as MTL and LNL),we've been assigning a "fake PCH" as a quickhack that allows us to avoid restructuring a bunch of the code.we've been assigning a "fake PCH" as a quick hack that allows us to avoid restructuring a bunch of the code. Removed unused macros of LNL amd MTL as well. v2: Reorder PCH_MTL conditional check (Matt Roper) Reverting to PCH_MTL for PICA interrupt(Matt Roper) Signed-off-by: Haridhar Kalvala <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-11-06drm/i915: Extract mchbar_reg()Ville Syrjälä1-13/+14
Stop repeating the same logic to determine the correct config space register for MCHBAR. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2023-10-05drm/i915/display: Created exclusive version of vga decode setupUma Shankar2-0/+16
Current vga arbiter implementation in i915 needs a re-design. The current approach would cause real problems if anyone actually needs to talk another GPU using legacy VGA resources. The main issue is that X becomes a slideshow if it thinks there are multiple GPUs that have VGA decoding enabled as it insists on adjusting the VGA routing pretty much for every little operation involving any of the GPUs. The cleanup will be planned for i915. Meanwhile to focus on Xe upstreaming and have a cleaner separation, the said functionality is being moved to a different file exclusive for i915. Xe driver will re-use rest of the display code from i915. v2: Addressed Jani Nikula's review comments. v3: Dropped a duplicate function (Jani) v4: Updated commit message with reasoning as sugested by Ville. Signed-off-by: Uma Shankar <[email protected]> Reviewed-by: Arun R Murthy <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-21drm/i915/xe2lpd: Add fake PCHGustavo Sousa2-1/+6
Xe2_LPD doesn't have south display engine on a PCH, it's actually on the SoC die (while north display engine is on compute die). As such it makes no sense to go through the PCI devices looking for an ISA bridge. The approach used by BXT/GLK can't be used here since leaving it with PCH_NONE would mean taking the wrong code paths. For the places we currently use a PCH check, it's enough for now to just check the north display version. Use that to define a fake PCH to be used across the driver. Eventually these PCH checks may need to be re-designed as this is already the third platform using/needing a fake PCH. v2: Match on display IP version rather than on platform (Matt Roper) v3: Extend and clarify commit message (Matt Roper / Ville) Signed-off-by: Gustavo Sousa <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-09-21drm/i915: Re-order if/else ladder in intel_detect_pch()Lucas De Marchi1-5/+8
Follow the convention of checking the last platform first and reword the comment to convey there are more platforms than just DG1. Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-07drm/i915/jsl: s/JSL/JASPERLAKE for platform/subplatform definesDnyaneshwar Bhadane1-3/+5
Follow consistent naming convention. Replace JSL with JASPERLAKE. Unroll IS_JSL_EHL() define with IS_JASPERLAKE() || IS_ELKHARTLAKE() condition. Change in the display step define for Jasperlake. v2: - Change subject prefix skl instead of SKL(Anusha) v3: - Remove the use of define IS_JSL_EHL. - Replace with IS_JASPERLAKE() || IS_ELKHARTLAKE() - Unrolled wrapper IS_JSL_ELK_DISPLAY_STEP (Jani/Tvrtko) v4: - Removed unused macro v5: - Resolved valid checkpatch warning(Jani) Cc: Tvrtko Ursulin <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Anusha Srivatsa <[email protected]> Signed-off-by: Dnyaneshwar Bhadane <[email protected]> Acked-by: Jani Nikula <[email protected]> Signed-off-by: Radhakrishna Sripada <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-07drm/i915/bdw: s/BDW/BROADWELL for platform/subplatform definesDnyaneshwar Bhadane1-5/+5
Follow consistent naming convention. Replace BDW with BROADWELL. Signed-off-by: Dnyaneshwar Bhadane <[email protected]> Reviewed-by: Anusha Srivatsa <[email protected]> Acked-by: Jani Nikula <[email protected]> Signed-off-by: Radhakrishna Sripada <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-07drm/i915/hsw: s/HSW/HASWELL for platform/subplatform definesDnyaneshwar Bhadane1-5/+5
Follow consistent naming convention. Replace HSW with HASWELL. Signed-off-by: Dnyaneshwar Bhadane <[email protected]> Reviewed-by: Anusha Srivatsa <[email protected]> Acked-by: Jani Nikula <[email protected]> Signed-off-by: Radhakrishna Sripada <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-07-04drm/i915/dram: replace __raw_uncore_read32() with intel_uncore_read_fw()Jani Nikula1-1/+1
The __raw_uncore_* interface is supposed to be intel_uncore.[ch] internal only. Replace the remaining outside user with intel_uncore_read_fw(), which is essentially the same thing. Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-06-13drm/i915/gmch: avoid unused variable warningArnd Bergmann1-3/+1
When CONFIG_PNP is disabled, the mchbar_addr variable is only written but not read: drivers/gpu/drm/i915/soc/intel_gmch.c: In function 'intel_alloc_mchbar_resource': drivers/gpu/drm/i915/soc/intel_gmch.c:41:13: error: variable 'mchbar_addr' set but not used [-Werror=unused-but-set-variable] 41 | u64 mchbar_addr; | ^~~~~~~~~~~ No idea why this showed up now, but it's easy to fix by changing the #ifdef to an IS_ENABLED() check that the compiler can see through. Signed-off-by: Arnd Bergmann <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Signed-off-by: Andi Shyti <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-02-15drm/i915: move memory frequency detection to intel_dram.cJani Nikula1-0/+152
The memory frequency detection is a bit spread out here and there. Consolidate to intel_dram.c. v2: - Remove inaccurate comment (Ville) - Call detect_mem_freq() unconditionally (Ville) Cc: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/8a862eeca8b42a98e04b3c52637851d33531abb6.1676317696.git.jani.nikula@intel.com
2023-01-25drm/i915/gmch: move VGA set state to GMCH codeJani Nikula2-0/+30
This is the only user for the GMCH bridge device in display. Move it to GMCH code. Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Acked-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/9bd50fe508246a547cf6e7abfe44ed686a4b3e3a.1673958757.git.jani.nikula@intel.com
2023-01-25drm/i915/gmch: mass rename dev_priv to i915Jani Nikula1-48/+47
Prefer the contemporary naming. Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Acked-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/3e4aaadeb4a027165f5724027963aa5e8d747190.1673958757.git.jani.nikula@intel.com
2023-01-25drm/i915/gmch: split out soc/intel_gmchJani Nikula2-0/+160
The GMCH related code is a bit too low level and out of place for the high level i915_driver.c file. Split out to a separate file under soc/. Rename the functions accordingly. Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Acked-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/980a5e08b397bc0dbccf93cd84798772233ce75c.1673958757.git.jani.nikula@intel.com
2022-12-13drm/i915: add new "soc" sub-directory and move PCH and DRAM code thereJani Nikula4-0/+956
Add a new sub-directory for things that aren't specifically about the GPU and don't really belong in the i915 driver top level, but also don't belong under any of the existing sub-directories either. Name it "soc", and move the PCH and DRAM code there. Cc: Joonas Lahtinen <[email protected]> Cc: Rodrigo Vivi <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Cc: Ville Syrjälä <[email protected]> Acked-by: Rodrigo Vivi <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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