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path: root/drivers/gpu/drm/i915/i915_suspend.c
AgeCommit message (Expand)AuthorFilesLines
2012-05-19drm/i915: gen6_enable_rps() wants to be called after ring initialisationChris Wilson1-6/+0
2012-05-03drm/i915: manage PCH PLLs separately from pipesJesse Barnes1-1/+1
2012-04-12drm/i915: re-init modeset hw state after gpu resetDaniel Vetter1-11/+1
2012-01-24drm/i915: Re-enable gen7 RC6 and GPU turbo after resume.Eric Anholt1-2/+2
2012-01-09drm/i915: handle 3rd pipeEugeni Dodonov1-0/+4
2012-01-09drm/i915: simplify pipe checkingEugeni Dodonov1-1/+2
2011-11-03drm/i915: Ivybridge still has fences!Daniel Vetter1-0/+2
2011-09-19Drivers: i915: Fix all space related issues.Akshay Joshi1-4/+4
2011-08-15drm/i915: Cannot set clock gating under UMSKeith Packard1-1/+2
2011-07-29Merge branch 'drm-intel-fixes' into drm-intel-nextKeith Packard1-0/+2
2011-07-29drm/i915/pch: Save/restore PCH_PORT_HOTPLUG across suspendAdam Jackson1-0/+2
2011-07-08drm/i915: Only export the generic intel_disable_fbc() interfaceChris Wilson1-3/+1
2011-06-29Merge branch 'drm-intel-fixes' into drm-intel-nextKeith Packard1-6/+13
2011-06-29drm/i915: Hold struct_mutex during i915_save_state/i915_restore_stateKeith Packard1-6/+13
2011-06-28drm/i915: load a ring frequency scaling table v3Jesse Barnes1-1/+3
2011-06-22drm/i915: save/resume forcewake lock fixesBen Widawsky1-0/+5
2011-05-13drm/i915: split PCH clock gating initJesse Barnes1-2/+1
2011-05-13drm/i915: split clock gating init into per-chipset functionsJesse Barnes1-1/+1
2011-03-23Revert "drm/i915: Don't save/restore hardware status page address register"Chris Wilson1-0/+6
2011-03-02drm/i915: Don't save/restore hardware status page address registerZhenyu Wang1-6/+0
2011-02-07drm/i915: cleanup per-pipe reg usageJesse Barnes1-215/+214
2011-01-11drm/i915: cleanup rc6 codeJesse Barnes1-4/+3
2011-01-11drm/i915: fix rc6 enabling around suspend/resumeJesse Barnes1-3/+0
2011-01-11drm/i915: re-enable rc6 support for Ironlake+Jesse Barnes1-2/+2
2010-12-20drm/i915: Undo "Uncouple render/power ctx before suspending"Chris Wilson1-0/+2
2010-12-18drm/i915: dynamic render p-state support for Sandy BridgeJesse Barnes1-2/+7
2010-12-05drm/i915: Uncouple render/power ctx before suspendingChris Wilson1-1/+3
2010-11-25drm/i915: Only save and restore fences for UMSChris Wilson1-43/+46
2010-11-21drm/i915: Only save/restore cursor regs if !KMSChris Wilson1-20/+20
2010-11-03i915: reprogram power monitoring registers on resumeKyle McMartin1-1/+3
2010-09-21drm/i915: INTEL_INFO->gen supercedes i8xx, i9xx, i965gChris Wilson1-12/+12
2010-09-21Merge branch 'drm-intel-fixes' into HEADChris Wilson1-9/+27
2010-09-18drm/i915: use GMBUS to manage i2c linksChris Wilson1-3/+1
2010-09-17drm/i915: Fix Sandybridge fence registersChris Wilson1-9/+27
2010-08-21drm/i915/suspend: s/IS_IRONLAKE/HAS_PCH_SPLIT/Chris Wilson1-37/+37
2010-08-21drm/i915/suspend: Flush register writes before busy-waiting.Chris Wilson1-9/+18
2010-08-01drm/i915: Add frame buffer compression support on Ironlake mobileZhao Yakui1-2/+7
2010-04-12drm/i915: Only save/restore FBC on the platform that supports FBCZhao Yakui1-19/+22
2010-02-22drm/i915: Deobfuscate the render p-state obfuscationMatthew Garrett1-2/+4
2010-02-22drm/i915: add dynamic performance control support for IronlakeJesse Barnes1-0/+8
2010-01-06drm/i915: Fix RC6 suspend/resumeAndrew Lutomirski1-12/+0
2009-12-10Merge remote branch 'anholt/drm-intel-next' into drm-linusDave Airlie1-6/+1
2009-12-08drm/i915: restore render clock gating on resumeAndrew Lutomirski1-6/+1
2009-12-08Merge remote branch 'anholt/drm-intel-next' into drm-linusDave Airlie1-36/+43
2009-12-07drm/i915: Fix product names and #definesAdam Jackson1-30/+30
2009-12-01drm/i915: Fix DDC on some systems by clearing BIOS GMBUS setup.Eric Anholt1-1/+4
2009-11-12drm/i915: Add more registers save/restore for Ironlake suspendZhenyu Wang1-1/+35
2009-11-05drm/i915: add render standby supportJesse Barnes1-2/+6
2009-10-23drm/i915: Ironlake suspend/resume supportZhenyu Wang1-55/+226
2009-10-15drm/i915: save/restore BLC histogram control reg across suspend/resumeJesse Barnes1-0/+2
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