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path: root/drivers/gpu/drm/i915/display/intel_ddi.c
AgeCommit message (Expand)AuthorFilesLines
2020-06-10drm/i915/tc: fix the reset of ln0Khaled Almahallawy1-1/+1
2020-06-04drm/i915/tgl: Add HBR and HBR2+ voltage swing tableJosé Roberto de Souza1-8/+42
2020-06-03drm/i915: Add {preemph,voltage}_max() vfuncsVille Syrjälä1-14/+7
2020-06-02drm/i915: Identify Cometlake platformChris Wilson1-10/+24
2020-06-01drm/i915/tgl: Update TC DP vswing tableJosé Roberto de Souza1-3/+3
2020-05-14drm/i915/psr: Use new DP VSC SDP compute routine on PSRGwan-gyeong Mun1-2/+2
2020-05-14drm/i915: Stop sending DP SDPs on ddi disableGwan-gyeong Mun1-0/+2
2020-05-14drm/i915: Program DP SDPs on pipe updatesGwan-gyeong Mun1-0/+1
2020-05-14drm/i915: Add state readout for DP VSC SDPGwan-gyeong Mun1-0/+1
2020-05-14drm/i915: Add state readout for DP HDR Metadata Infoframe SDPGwan-gyeong Mun1-0/+8
2020-05-14drm/i915: Program DP SDPs with computed configsGwan-gyeong Mun1-2/+1
2020-05-11drm/i915: Use stashed away hpd isr bits in intel_digital_port_connected()Ville Syrjälä1-78/+10
2020-05-11drm/i915: Turn intel_digital_port_connected() in a vfuncVille Syrjälä1-0/+109
2020-04-24drm/i915: Split some long linesVille Syrjälä1-2/+8
2020-04-24drm/i915: Introduce .set_idle_link_train() vfuncVille Syrjälä1-0/+29
2020-04-24drm/i915: Introduce .set_signal_levels() vfuncVille Syrjälä1-20/+59
2020-04-24drm/i915: Introduce .set_link_train() vfuncVille Syrjälä1-0/+42
2020-04-21drm/i915/display/ddi: Prefer drm_WARN* over WARN*Pankaj Bharadiya1-6/+8
2020-04-21drm/i915: drop a bunch of superfluous inlinesJani Nikula1-4/+3
2020-04-20drm/i915: Pass encoder all the way to intel_ddi_transcoder_func_reg_val_get()Ville Syrjälä1-29/+10
2020-04-20drm/i915: Push TRANS_DDI_FUNC_CTL into the encoder->enable() hookVille Syrjälä1-0/+2
2020-04-20drm/i915: Pass encoder to intel_ddi_enable_pipe_clock()Ville Syrjälä1-5/+5
2020-04-17drm/i915/display: Load DP_TP_CTL/STATUS offset before use itJosé Roberto de Souza1-3/+11
2020-04-06drm/i915: Extend hotplug detect retry on TypeC connectors to 5 secondsImre Deak1-1/+11
2020-04-06drm/i915: Add a retry counter for hotplug detect retriesImre Deak1-4/+3
2020-04-03drm/i915: Move the port sync DP_TP_CTL stuff to the encoder hookVille Syrjälä1-0/+37
2020-04-03drm/i915: Pass atomic state to encoder hooksVille Syrjälä1-33/+56
2020-04-03drm/i915: Implement port sync for SKL+Ville Syrjälä1-19/+51
2020-04-03drm/i915: Store cpu_transcoder_mask in device infoVille Syrjälä1-3/+3
2020-03-31drm/i915/tc/icl: Update TC vswing tablesJosé Roberto de Souza1-20/+73
2020-03-31drm/i915/dp/ehl: Update vswing table for HBR and RBRJosé Roberto de Souza1-5/+4
2020-03-31drm/i915/dp: Return the right vswing tablesJosé Roberto de Souza1-2/+3
2020-03-31drm/i915/icl+: Don't enable DDI IO power on a TypeC port in TBT modeImre Deak1-1/+5
2020-03-27drm/i915: Use REG_FIELD_PREP() & co. for TRANS_DDI_FUNC_CTL2Ville Syrjälä1-4/+2
2020-03-27drm/i915: Move icl_get_trans_port_sync_config() into the DDI codeVille Syrjälä1-0/+54
2020-03-27drm/i915: Move TRANS_DDI_FUNC_CTL2 programming where it belongsVille Syrjälä1-33/+40
2020-03-25drm/i915/ddi: use struct drm_device based loggingJani Nikula1-46/+72
2020-03-05drm/i915/display: Decrease log levelSwati Sharma1-2/+3
2020-03-04drm/i915/ehl: Check PHY type before reading DPLL frequencyMatt Roper1-1/+2
2020-03-02drm/i915/skl, cnl: Split out the WRPLL/LCPLL frequency calculationImre Deak1-2/+2
2020-03-02drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.cImre Deak1-432/+10
2020-03-02drm/i915/hsw: Use the DPLL ID when calculating DPLL clockImre Deak1-9/+8
2020-03-02drm/i915: Keep the global DPLL state in a DPLL specific structImre Deak1-6/+6
2020-02-23drm/i915/display/ddi: Make WARN* drm specific where drm_device ptr is availablePankaj Bharadiya1-41/+51
2020-02-20drm/i915/dp: Compute port sync crtc states post compute_config()Manasi Navare1-0/+107
2020-02-15drm/i915/mst: Set intel_dp_set_m_n() for MST slavesJosé Roberto de Souza1-2/+3
2020-02-10drm/i915/tgl: Update cdclk voltage level settingsMatt Roper1-1/+3
2020-02-10drm/i915/ehl: Update port clock voltage level requirementsMatt Roper1-1/+3
2020-02-10drm/i915/display/ehl: Add HBR2 and HBR3 voltage swing tableJosé Roberto de Souza1-1/+33
2020-02-06drm/i915/display: Set TRANS_DDI_MODE_SELECT to default value when clearing DD...José Roberto de Souza1-4/+7
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