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path: root/drivers/gpu/drm/i915/display/intel_ddi.c
AgeCommit message (Expand)AuthorFilesLines
2020-10-30drm/i915: Give DDI encoders even better namesVille Syrjälä1-2/+25
2020-10-30drm/i915: Add PORT_TCn aliases to enum portVille Syrjälä1-6/+6
2020-10-23drm/i915/dg1: add hpd interrupt handlingLucas De Marchi1-1/+12
2020-10-20drm/i915: s/intel_dp_sink_dpms/intel_dp_set_power/Ville Syrjälä1-3/+3
2020-10-14drm/i915/jsl: Split EHL/JSL platform info and PCI idsTejas Upadhyay1-6/+6
2020-10-12drm/i915: Fix DP link training pattern maskImre Deak1-2/+1
2020-10-09drm/i915: Wait for eDP panel power cycle delay on reboot on all platformsVille Syrjälä1-0/+1
2020-10-07drm/i915/display/ehl: Limit eDP to HBR2José Roberto de Souza1-7/+2
2020-10-06drm/i915: Add an encoder hook to sanitize its state during init/resumeImre Deak1-0/+8
2020-10-06drm/i915: Move the initial fastset commit check to encoder hooksImre Deak1-0/+10
2020-10-01drm/i915: Init lspcon after HPD in intel_dp_detect()Kai-Heng Feng1-18/+1
2020-10-01drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl,status}Ville Syrjälä1-50/+57
2020-10-01drm/i915: Plumb crtc_state to link trainingVille Syrjälä1-213/+200
2020-10-01drm/i915: Split TGL DKL PHY buf trans per output typeVille Syrjälä1-8/+23
2020-10-01drm/i915: Split TGL combo PHY buf trans per output typeVille Syrjälä1-34/+49
2020-10-01drm/i915: Split EHL combo PHY buf trans per output typeVille Syrjälä1-20/+39
2020-10-01drm/i915: Split ICL MG PHY buf trans per output typeVille Syrjälä1-8/+23
2020-10-01drm/i915: Split ICL combo PHY buf trans per output typeVille Syrjälä1-9/+33
2020-10-01drm/i915: Fix TGL DKL PHY DP vswing handlingVille Syrjälä1-1/+1
2020-09-17drm/i915: Configure DP 1.3+ protocol converted HDMI modeVille Syrjälä1-0/+1
2020-09-17drm/i915/lspcon: Do not send infoframes to non-HDMI sinksVille Syrjälä1-6/+4
2020-09-15drm/i915: Introduce HPD_PORT_TC<n>Ville Syrjälä1-1/+64
2020-09-15drm/i915: Move hpd_pin setup to encoder initVille Syrjälä1-0/+1
2020-09-11Merge drm/drm-next into drm-intel-next-queuedRodrigo Vivi1-2/+2
2020-09-08Merge tag 'v5.9-rc4' into drm-nextDave Airlie1-2/+2
2020-09-01drm/i915: Use ddi_update_pipe in intel_dp_mstSean Paul1-5/+6
2020-09-01drm/i915: Don't fully disable HDCP on a port if multiple pipes are using itSean Paul1-0/+3
2020-09-01drm/i915: Use the cpu_transcoder in intel_hdcp to toggle HDCP signallingSean Paul1-10/+3
2020-09-01drm/i915: WARN if HDCP signalling is enabled upon disableSean Paul1-0/+2
2020-08-28drm/i915/ehl: Update voltage swing tableJosé Roberto de Souza1-5/+5
2020-08-28drm/i915/display/ehl: Use EHL DP tables for eDP ports without low power supportJosé Roberto de Souza1-3/+19
2020-08-28drm/i915/display/tgl: Use TGL DP tables for eDP ports without low power supportJosé Roberto de Souza1-19/+33
2020-08-27drm/i915/display: Disable DRRS when needed in fastsetsJosé Roberto de Souza1-1/+1
2020-08-23treewide: Use fallthrough pseudo-keywordGustavo A. R. Silva1-2/+2
2020-08-17drm/i915/tgl: Add new voltage swing tableJosé Roberto de Souza1-0/+19
2020-08-17drm/i915/rkl: Handle HTIMatt Roper1-0/+19
2020-08-17drm/i915/rkl: Handle new DPCLKA_CFGCR0 layoutMatt Roper1-3/+15
2020-08-17drm/i915/display: Implement HOBLJosé Roberto de Souza1-0/+43
2020-08-17drm/i915/ddi: Don't rewrite DDI_BUF_CTL reg during DP link trainingImre Deak1-4/+0
2020-08-17drm/i915/ddi: Don't frob the DP link scramble disabling flagImre Deak1-7/+1
2020-07-09drm/i915/display: Remove port and phy from voltage swing functionsJosé Roberto de Souza1-19/+14
2020-07-09drm/i915/display: Replace drm_i915_private in voltage swing functions by inte...José Roberto de Souza1-69/+95
2020-07-08drm/i915/dp: Helper to check for DDI BUF status to get activeManasi Navare1-1/+16
2020-07-08drm/i915/dp: Helper for checking DDI_BUF_CTL Idle statusManasi Navare1-9/+8
2020-07-02drm/i915/display: prefer dig_port to reference intel_digital_portLucas De Marchi1-73/+70
2020-06-30drm/i915/display: remove alias to dig_portLucas De Marchi1-6/+5
2020-06-24drm/i915/dp_mst: Enable VC payload allocation after transcoder is enabledImre Deak1-5/+3
2020-06-23drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encodersImre Deak1-5/+10
2020-06-12drm/i915/display: Fix the encoder type checkVandita Kulkarni1-3/+3
2020-06-11drm/i915/icl: Disable DIP on MST ports with the transcoder clock still onImre Deak1-1/+3
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