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path: root/drivers/gpu/drm/i915/display/intel_cdclk.h
AgeCommit message (Expand)AuthorFilesLines
2023-01-25drm/i915/display: add intel_display_limits.h for key enumsJani Nikula1-1/+1
2022-08-31drm/i915: move and group cdclk under display.cdclkJani Nikula1-2/+2
2022-03-21drm/i915: Fix DBUF bandwidth vs. cdclk handlingVille Syrjälä1-0/+2
2022-01-24drm/i915/cdclk: update intel_dump_cdclk_config() loggingJani Nikula1-1/+2
2021-12-14drm/i915/cdclk: turn around i915_drv.h and intel_cdclk.h dependencyJani Nikula1-1/+5
2021-12-13drm/i915/cdclk: hide struct intel_cdclk_valsJani Nikula1-8/+0
2021-12-13drm/i915/cdclk: move intel_atomic_check_cdclk() to intel_cdclk.cJani Nikula1-1/+2
2021-12-07drm/i915/display/dg2: Introduce CD clock squashing tableMika Kahola1-0/+1
2021-09-29drm/i915: add wrappers around cdclk vtable funcs.Dave Airlie1-1/+3
2020-09-17drm/i915: Nuke force_min_cdclk_changedVille Syrjälä1-1/+0
2020-08-17drm/i915: Pack struct intel_cdclk_valsVille Syrjälä1-1/+1
2020-02-19drm/i915: Read rawclk_freq earlierChris Wilson1-1/+1
2020-01-31drm/i915: Store active_pipes bitmask in cdclk stateVille Syrjälä1-0/+3
2020-01-31drm/i915: Convert cdclk to global stateVille Syrjälä1-3/+42
2020-01-31drm/i915: s/init_cdclk/init_cdclk_hw/Ville Syrjälä1-2/+2
2020-01-31drm/i915: Simplify intel_set_cdclk_{pre,post}_plane_update() calling conventionVille Syrjälä1-10/+2
2020-01-31drm/i915: s/cdclk_state/cdclk_config/Ville Syrjälä1-9/+9
2020-01-31drm/i915: Collect more cdclk state under the same roofVille Syrjälä1-0/+1
2019-09-16drm/i915: Extract intel_modeset_calc_cdclk()Ville Syrjälä1-5/+1
2019-09-10drm/i915: Use literal representation of cdclk tablesMatt Roper1-0/+7
2019-06-17drm/i915: move modesetting core code under display/Jani Nikula1-0/+46
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