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path: root/drivers/gpu/drm/amd/display/dc/resource
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2024-10-01drm/amd/display: avoid set dispclk to 0Charlene Liu1-0/+1
[why] set dispclk to 0 cause stability issue. Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> (cherry picked from commit 1c6b16ebf5eb2bc5740be9e37b3a69f1dfe1dded) Cc: [email protected]
2024-09-18drm/amd/display: Disable SYMCLK32_LE root clock gatingSung Joon Kim1-1/+1
[WHY & HOW] On display on sequence, enabling SYMCLK32_LE root clock gating causes issue in link training so disabling it is needed. Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-09-18drm/amd/display: Enable DML2 override_det_buffer_size_kbytesYihan Zhu2-0/+2
[WHY] Corrupted screen will be observed when 4k144 DP/HDMI display and 4k144 eDP are connected, changing eDP refresh rate from 60Hz to 144Hz. [HOW] override_det_buffer_size_kbytes should be true for DCN35/DCN351. Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Reviewed-by: Roman Li <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Yihan Zhu <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-09-02Revert "drm/amd/display: Wait for all pending cleared before full update"Dillon Varone2-5/+3
This reverts commit f0b7dcf25834afd17df316367dfe5d4c890c713c. It is causing graphics hangs. Reviewed-by: Martin Leung <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-08-27drm/amd/display: add back quality EASF and ISHARP and dc dependency changesSamson Tam1-0/+7
[Why] Addressed previous issues with quality changes and new issues due to rolling back quality changes. [How] This reverts commit f9e6759888866748f31b6b6c2142a481d587f51f, fixes merge conflicts, and fixed some formatting errors. Store current sharpness level for each pregen table to minimize calculating sharpness table every time. Disable dynamic ODM when sharpness is enabled. Reviewed-by: Jun Lei <[email protected]> Signed-off-by: Samson Tam <[email protected]> Signed-off-by: Zaeem Mohamed <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-08-27drm/amd/display: Wait for all pending cleared before full updateAlvin Lee2-3/+5
[Description] Before every full update we must wait for all pending updates to be cleared - this is particularly important for minimal transitions because if we don't wait for pending cleared, it will be as if there was no minimal transition at all. In OTG we must read 3 different status registers for pending cleared, one specifically for OTG updates, one specifically for OPTC updates, and the last for surface related updates Reviewed-by: Dillon Varone <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Zaeem Mohamed <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-08-20drm/amd/display: DCN35 set min dispclk to 50MhzNicholas Susanto1-0/+1
[Why] Causes hard hangs when resuming after display off on extended/duplicate modes [How] Set the min dispclk to 50Mhz for DCN35 Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Nicholas Susanto <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-08-13drm/amd/display: Enable otg synchronization logic for DCN321Loan Chen1-0/+3
[Why] Tiled display cannot synchronize properly after S3. The fix for commit 5f0c74915815 ("drm/amd/display: Fix for otg synchronization logic") is not enable in DCN321, which causes the otg is excluded from synchronization. [How] Enable otg synchronization logic in dcn321. Fixes: 5f0c74915815 ("drm/amd/display: Fix for otg synchronization logic") Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Loan Chen <[email protected]> Signed-off-by: Tom Chung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-08-13drm/amd/display: Set max VTotal cap for dcn401Dillon Varone1-0/+1
[WHY&HOW] Set max VTotal cap for dcn401 because VTotal register is only 16 bits wide on dcn401. Reviewed-by: Chris Park <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Tom Chung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-08-06drm/amd/display: Force enable 3DLUT DMA check for dcn401 in DMLDillon Varone1-0/+1
[WHY] Currently TR0 (trip 0) is not properly budgeting for urgent latency in DML2.1. This results in overly aggressive prefetch schedules that are vulnerable to request return jitter, resulting in severe underflow at the start of the frame. [HOW] Forcing 3DLUT DMA check to enable causes urgent latency to be budgeted properly into the prefetch schedule, avoiding the vulnerability. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-08-06drm/amd/display: Cleanup dml2 and dc/resource MakefileRodrigo Siqueira1-2/+0
Remove some useless lines from DC Makefiles. Acked-by: Tom Chung <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-08-06drm/amd/display: Add missing registers for dcn32Rodrigo Siqueira1-0/+5
Add missing debug registers for DCN32. Reviewed-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-08-06drm/amd/display: Add dcc propagation valueRodrigo Siqueira1-0/+1
Initialize the field dcc_meta_propagation_delay_us with 10 ms. Reviewed-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-08-06drm/amd/display: Add missing mcache registersRodrigo Siqueira1-1/+3
Add missing register programming for mcache in DCN401. Reviewed-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-27drm/amd/display: Fix possible overflow in integer multiplicationAlex Hung1-2/+2
[WHAT & HOW] Integer multiplies integer may overflow in context that expects an expression of unsigned long long (64 bits). This can be fixed by casting integer to unsigned long long to force 64 bits results. This fixes 2 OVERFLOW_BEFORE_WIDEN issues reported by Coverity. Signed-off-by: Alex Hung <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-27drm/amd/display: roll back quality EASF and ISHARP and dc dependency changesSamson Tam1-7/+0
[Why] Seeing several regressions related to quality EASF and ISHARP changes and removing dc dependency changes. [How] Roll back SPL changes Signed-off-by: Samson Tam <[email protected]> Reviewed-by: Martin Leung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Add null check for head_pipe in ↵Srinivasan Shanmugam1-1/+3
dcn32_acquire_idle_pipe_for_head_pipe_in_layer This commit addresses a potential null pointer dereference issue in the `dcn32_acquire_idle_pipe_for_head_pipe_in_layer` function. The issue could occur when `head_pipe` is null. The fix adds a check to ensure `head_pipe` is not null before asserting it. If `head_pipe` is null, the function returns NULL to prevent a potential null pointer dereference. Reported by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn32/dcn32_resource.c:2690 dcn32_acquire_idle_pipe_for_head_pipe_in_layer() error: we previously assumed 'head_pipe' could be null (see line 2681) Cc: Tom Chung <[email protected]> Cc: Rodrigo Siqueira <[email protected]> Cc: Roman Li <[email protected]> Cc: Alex Hung <[email protected]> Cc: Aurabindo Pillai <[email protected]> Cc: Harry Wentland <[email protected]> Cc: Hamza Mahfooz <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Tom Chung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Add null check for head_pipe in ↵Srinivasan Shanmugam1-1/+3
dcn201_acquire_free_pipe_for_layer This commit addresses a potential null pointer dereference issue in the `dcn201_acquire_free_pipe_for_layer` function. The issue could occur when `head_pipe` is null. The fix adds a check to ensure `head_pipe` is not null before asserting it. If `head_pipe` is null, the function returns NULL to prevent a potential null pointer dereference. Reported by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn201/dcn201_resource.c:1016 dcn201_acquire_free_pipe_for_layer() error: we previously assumed 'head_pipe' could be null (see line 1010) Cc: Tom Chung <[email protected]> Cc: Rodrigo Siqueira <[email protected]> Cc: Roman Li <[email protected]> Cc: Alex Hung <[email protected]> Cc: Aurabindo Pillai <[email protected]> Cc: Harry Wentland <[email protected]> Cc: Hamza Mahfooz <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Tom Chung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Implement bounds check for stream encoder creation in DCN401Srinivasan Shanmugam1-1/+1
'stream_enc_regs' array is an array of dcn10_stream_enc_registers structures. The array is initialized with four elements, corresponding to the four calls to stream_enc_regs() in the array initializer. This means that valid indices for this array are 0, 1, 2, and 3. The error message 'stream_enc_regs' 4 <= 5 below, is indicating that there is an attempt to access this array with an index of 5, which is out of bounds. This could lead to undefined behavior Here, eng_id is used as an index to access the stream_enc_regs array. If eng_id is 5, this would result in an out-of-bounds access on the stream_enc_regs array. Thus fixing Buffer overflow error in dcn401_stream_encoder_create Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn401/dcn401_resource.c:1209 dcn401_stream_encoder_create() error: buffer overflow 'stream_enc_regs' 4 <= 5 Cc: Tom Chung <[email protected]> Cc: Rodrigo Siqueira <[email protected]> Cc: Roman Li <[email protected]> Cc: Alex Hung <[email protected]> Cc: Aurabindo Pillai <[email protected]> Cc: Harry Wentland <[email protected]> Cc: Hamza Mahfooz <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Tom Chung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Check null pointers before multiple usesAlex Hung3-6/+12
[WHAT & HOW] Poniters, such as stream_enc and dc->bw_vbios, are null checked previously in the same function, so Coverity warns "implies that stream_enc and dc->bw_vbios might be null". They are used multiple times in the subsequent code and need to be checked. This fixes 10 FORWARD_NULL issues reported by Coverity. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Add P-State Keepout to dcn401 Global SyncDillon Varone2-1/+3
[WHY&HOW] OTG has new functionality to allow P-State relative to VStartup. Keepout region for this should be configured based on DML outputs same as other global sync params. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Pass non-null to dcn20_validate_apply_pipe_split_flagsAlex Hung2-2/+4
[WHAT & HOW] "dcn20_validate_apply_pipe_split_flags" dereferences merge, and thus it cannot be a null pointer. Let's pass a valid pointer to avoid null dereference. This fixes 2 FORWARD_NULL issues reported by Coverity. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Check phantom_stream before it is usedAlex Hung1-0/+3
dcn32_enable_phantom_stream can return null, so returned value must be checked before used. This fixes 1 NULL_RETURNS issue reported by Coverity. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: quality improvements for EASF and ISHARPSamson Tam1-0/+7
[Why] Update coefficients and LUT tables for scaler and sharpener to improve quality and support different use cases (SDR/HDR) [How] Move scaler coefficients to new file dc_spl_scl_easf_filters.c Remove older coefficients file dc_sp_scl_filters_old.c Update default taps for EASF support Update LLS policy for DON'T CARE case Update cositing offset from 0.5 to 0.25 Add support to adjust sharpness based on level, use case, and scaling ratio ( using discrete levels ) Apply sharpness to all RGB surfaces and both NV12 and P010 video ( in fullscreen only ). Upscale and 1:1 ratios only Enable scaler when sharpening 1:1 ratios Add support for coefficients that are in S1.10 format (convert to S1.12 format) Reviewed-by: Jun Lei <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Samson Tam <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Disable HBR audio for DP2 for certain ASICsAlvin Lee4-0/+4
[Description] Due to a HW bug, HBR audio is not supported for DP2 encoders for certain ASICs. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-01drm/amd/display: un-block 8k with single dimmPaul Hsieh1-22/+0
[Why] Driver doesn't validate multi-display with scaling when OS calls DDI. This behavior causes the validated result to be a mismatch between some automated test cases. To address this issue, some workaround was added that caused issues in 8k. [How] Since the origin issue had been root caused, revert the previous workaround and unblock 8k with a single dimm. Reviewed-by: Aric Cyr <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Paul Hsieh <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-01drm/amd/display: Check denominator crb_pipes before usedAlex Hung1-1/+1
[WHAT & HOW] A denominator cannot be 0, and is checked before used. This fixes 2 DIVIDE_BY_ZERO issues reported by Coverity. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-01drm/amd/display: Add ASIC cap to limit DCC surface widthGeorge Shen1-0/+3
[Why] Certain configurations of DCN401 require ODM4:1 to support DCC for 10K surfaces. DCC should be conservatively disabled in those cases. The issue is that current logic limits 10K surface DCC for all configurations of DCN401. [How] Add DC ASIC cap to indicate max surface width that can support DCC. Disable DCC if this ASIC cap is non-zero and surface width exceeds it. Reviewed-by: Jun Lei <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: George Shen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-01drm/amd/display: Revert Add workaround to restrict max frac urgent for DPM0Teeger1-2/+0
This reverts commit 871512e36f9c1c2cb4e62eb860ca0438800e4d63 due to multiple issues found. Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Teeger <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-27drm/amd/display: Fix null pointer deref in dcn20_resource.cAurabindo Pillai1-4/+5
Fixes a hang thats triggered when MPV is run on a DCN401 dGPU: mpv --hwdec=vaapi --vo=gpu --hwdec-codecs=all and then enabling fullscreen playback (double click on the video) The following calltrace will be seen: [ 181.843989] BUG: kernel NULL pointer dereference, address: 0000000000000000 [ 181.843997] #PF: supervisor instruction fetch in kernel mode [ 181.844003] #PF: error_code(0x0010) - not-present page [ 181.844009] PGD 0 P4D 0 [ 181.844020] Oops: 0010 [#1] PREEMPT SMP NOPTI [ 181.844028] CPU: 6 PID: 1892 Comm: gnome-shell Tainted: G W OE 6.5.0-41-generic #41~22.04.2-Ubuntu [ 181.844038] Hardware name: System manufacturer System Product Name/CROSSHAIR VI HERO, BIOS 6302 10/23/2018 [ 181.844044] RIP: 0010:0x0 [ 181.844079] Code: Unable to access opcode bytes at 0xffffffffffffffd6. [ 181.844084] RSP: 0018:ffffb593c2b8f7b0 EFLAGS: 00010246 [ 181.844093] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000004 [ 181.844099] RDX: ffffb593c2b8f804 RSI: ffffb593c2b8f7e0 RDI: ffff9e3c8e758400 [ 181.844105] RBP: ffffb593c2b8f7b8 R08: ffffb593c2b8f9c8 R09: ffffb593c2b8f96c [ 181.844110] R10: 0000000000000000 R11: 0000000000000000 R12: ffffb593c2b8f9c8 [ 181.844115] R13: 0000000000000001 R14: ffff9e3c88000000 R15: 0000000000000005 [ 181.844121] FS: 00007c6e323bb5c0(0000) GS:ffff9e3f85f80000(0000) knlGS:0000000000000000 [ 181.844128] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 181.844134] CR2: ffffffffffffffd6 CR3: 0000000140fbe000 CR4: 00000000003506e0 [ 181.844141] Call Trace: [ 181.844146] <TASK> [ 181.844153] ? show_regs+0x6d/0x80 [ 181.844167] ? __die+0x24/0x80 [ 181.844179] ? page_fault_oops+0x99/0x1b0 [ 181.844192] ? do_user_addr_fault+0x31d/0x6b0 [ 181.844204] ? exc_page_fault+0x83/0x1b0 [ 181.844216] ? asm_exc_page_fault+0x27/0x30 [ 181.844237] dcn20_get_dcc_compression_cap+0x23/0x30 [amdgpu] [ 181.845115] amdgpu_dm_plane_validate_dcc.constprop.0+0xe5/0x180 [amdgpu] [ 181.845985] amdgpu_dm_plane_fill_plane_buffer_attributes+0x300/0x580 [amdgpu] [ 181.846848] fill_dc_plane_info_and_addr+0x258/0x350 [amdgpu] [ 181.847734] fill_dc_plane_attributes+0x162/0x350 [amdgpu] [ 181.848748] dm_update_plane_state.constprop.0+0x4e3/0x6b0 [amdgpu] [ 181.849791] ? dm_update_plane_state.constprop.0+0x4e3/0x6b0 [amdgpu] [ 181.850840] amdgpu_dm_atomic_check+0xdfe/0x1760 [amdgpu] Signed-off-by: Aurabindo Pillai <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-27drm/amd/display: Enable DCC on DCN401Aurabindo Pillai2-0/+11
[WHAT] Add registers and entry points to enable DCC on DCN4x Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-27drm/amd/display: Add workaround to restrict max frac urgent for DPM0Sung-huai Wang1-1/+2
[WHY] Underflow occurs on some platforms when urgent BW is close to the maximum in DPM0. [HOW] It does not occur at DPM1, so as a workaround restrict the maximum amount and increase the lowest state index for clock states until we're out of DPM0. Adds DML2 config options to specify this pe platform as required. Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Sung-huai Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-27drm/amd/display: Temporarily disable HPO PG on DCN35Nicholas Susanto1-1/+1
[WHY] On hotpluggin a 4k144 HDMI FRL setup, display fails FRL link training and falls back to TMDS which is caused by driver not ungating HPO before doing FRL link training. [HOW] Enable debug flag to disable HPO power gate in DCN35 Reviewed-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Nicholas Susanto <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-19drm/amd/display: Check dc_stream_state before it is usedAlex Hung1-0/+2
dc_state_get_stream_status dc_state_get_paired_subvp_stream and other functions can return null, and therefore null must be checked before status can be used. This fixes 21 NULL_RETURNS issues reported by Coverity. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-19drm/amd/display: Add null checker before access structsAlex Hung2-2/+4
Checks null pointer before accessing various structs. This fixes 5 NULL_RETURNS issues reported by Coverity. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Send message to notify the DPIA host router bandwidthSung Joon Kim1-0/+1
[why] Tell the system about the current host router bandwidth to be used to measure and calculate the right voltage to be used. [how] Send SMU message of each DPIA host router bandwidth. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Refactor DCN3X into component folderMounika Adhuri2-1/+781
[why] Move DCN3X files to unique component folder. [how] Create respective component folder in dc, move the DCN3X files into corresponding new folders and made appropriate changes for compilation in Makefiles. Reviewed-by: Martin Leung <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Mounika Adhuri <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14Revert "drm/amd/display: workaround for oled eDP not lighting up on DCN401"Joshua Aberback1-1/+0
This reverts commit e902dd7f3e3b93a401e1d3c0322cce933e75e809. A proper fix for this issue has been implemented in DMUB FW. So, no need to keep the workaround. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Joshua Aberback <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Enable DCN401 idle optimizations by defaultDillon Varone1-1/+0
[WHY&HOW] Re-enable idle optimizations by default. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: DCN401 full power down in HW init if any link enabledJoshua Aberback1-1/+0
[Why] During HW init, certain operations the driver performs are invalid on enabled hardware in an unknown state (for example, setting all clock values to minimum when the GPU is actively driving a display). There is already code present to call HWSS->power_down during init when any link is enabled in HW, but that function pointer is unpopulated for most asics. We want to enable this codepath for DCN401, as it resolves the issue with being unable to drive certain display configs on adapter re-enable, and we can restore boot optimizations. [How] - add power_down HWSS function for DCN401 - remove debug bit to disable boot optimizations for DCN401 Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Joshua Aberback <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Disable PHYSYMCLK RCODaniel Miess2-2/+2
[Why] PHYSYMCLK RCO has been found to lead to crashes in some corner cases [How] Disable PHYSYMCLK RCO debug bit Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Daniel Miess <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Disable DMCUB timeout for DCN35Nicholas Kazlauskas1-0/+1
[Why] DMCUB can intermittently take longer than expected to process commands. Old ASIC policy was to continue while logging a diagnostic error - which works fine for ASIC without IPS, but with IPS this could lead to a race condition where we attempt to access DCN state while it's inaccessible, leading to a system hang when the NIU port is not disabled or register accesses that timeout and the display configuration in an undefined state. [How] We need to investigate why these accesses take longer than expected, but for now we should disable the timeout on DCN35 to avoid this race condition. Since the waits happen only at lower interrupt levels the risk of taking too long at higher IRQ and causing a system watchdog timeout are minimal. Reviewed-by: Ovidiu Bunea <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Disable boot optimization for DCN401Joshua Aberback1-0/+1
[Why] DCN401 currently has an issue re-enabling when pipe splitting is enabled, while the root cause is being investigated we can make sure everything is being reset as a workaround, by disabling boot optimization. [How] - use enable_accelerated_mode instead of init_pipes to fully reset asic Reviewed-by: Alvin Lee <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Joshua Aberback <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Add sequential ONO sequencing for DCN35Nicholas Kazlauskas1-0/+4
[Why] Adds support for performing the sequential ONO changes from DCN351 into DCN35 ASIC based on revision. [How] Check the revision and run the DCN351 sequences on applicable revisions. Reviewed-by: Sung joon Kim <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Remove redundant ternary operationIvan Lipski1-1/+1
[WHY] Coverity analysis flagged this ternary operation as DEADCODE. Since 'total_y_free_entry' is initialized as 0x200 and 'total_c_free_entry' is initialized as 0x140, and they never change values before the ternary operator, so 'total_y_free_entry' is always greater 'total_c_free_entry', 'so small_free_entry' is always set to 'total_c_free_entry'. [HOW] Replace the ternary operator with the variable declaration. Signed-off-by: Ivan Lipski <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Remove unreachable checkIvan Lipski2-5/+0
[WHY] Coverity analysis flagged this code as DEADCODE since the condition and return in the outer loop are never reached. All operations with the 'dwb_pipe' variable happen in the inner loop, that already contains the same check with the 'MAX_DWB_PIPES'. The later check condition cannot occur before the check condition in the inner loop, thus the later condition is unreacable. [HOW] Remove the unreachable condition. Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display/dcn401: use pre-allocated temp structure for bounding boxAlex Deucher1-6/+2
This mirrors what the driver does for older DCN generations. Should fix: [ 26.924055] BUG: sleeping function called from invalid context at include/linux/sched/mm.h:306 [ 26.924060] in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 1022, name: modprobe [ 26.924063] preempt_count: 2, expected: 0 [ 26.924064] RCU nest depth: 0, expected: 0 [ 26.924066] Preemption disabled at: [ 26.924067] [<ffffffffc089e5e0>] dc_fpu_begin+0x30/0xd0 [amdgpu] [ 26.924322] CPU: 9 PID: 1022 Comm: modprobe Not tainted 6.8.0+ #20 [ 26.924325] Hardware name: System manufacturer System Product Name/CROSSHAIR VI HERO, BIOS 6302 10/23/2018 [ 26.924326] Call Trace: [ 26.924327] <TASK> [ 26.924329] dump_stack_lvl+0x37/0x50 [ 26.924333] ? dc_fpu_begin+0x30/0xd0 [amdgpu] [ 26.924589] dump_stack+0x10/0x20 [ 26.924592] __might_resched+0x16a/0x1c0 [ 26.924596] __might_sleep+0x42/0x70 [ 26.924598] __kmalloc_node_track_caller+0x2ad/0x4b0 [ 26.924601] ? dm_helpers_allocate_gpu_mem+0x12/0x20 [amdgpu] [ 26.924855] ? dcn401_update_bw_bounding_box+0x2a/0xf0 [amdgpu] [ 26.925122] kmemdup+0x20/0x50 [ 26.925124] ? kernel_fpu_begin_mask+0x6b/0xe0 [ 26.925127] ? kmemdup+0x20/0x50 [ 26.925129] dcn401_update_bw_bounding_box+0x2a/0xf0 [amdgpu] [ 26.925393] dc_create+0x311/0x670 [amdgpu] [ 26.925649] amdgpu_dm_init+0x2aa/0x1fa0 [amdgpu] [ 26.925903] ? irq_work_queue+0x38/0x50 [ 26.925907] ? vprintk_emit+0x1e7/0x270 [ 26.925910] ? dev_printk_emit+0x83/0xb0 [ 26.925914] ? amdgpu_device_rreg+0x17/0x20 [amdgpu] [ 26.926133] dm_hw_init+0x14/0x30 [amdgpu] v2: drop extra memcpy Fixes: 669d6b078ed8 ("drm/amd/display: avoid large on-stack structures") Reviewed-by: Harry Wentland <[email protected]> Acked-by: Arnd Bergmann <[email protected]> Suggested-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: George Zhang <[email protected]> Cc: Arnd Bergmann <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected]
2024-06-14drm/amd/display: use pre-allocated temp structure for bounding boxAlex Deucher2-12/+4
This mirrors what the driver does for older DCN generations. Should fix: BUG: sleeping function called from invalid context at include/linux/sched/mm.h:306 in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 449, name: kworker/u64:8 preempt_count: 2, expected: 0 RCU nest depth: 0, expected: 0 Preemption disabled at: ffffffffc0ce1580>] dc_fpu_begin+0x30/0xd0 [amdgpu] CPU: 5 PID: 449 Comm: kworker/u64:8 Tainted: G W 6.8.0+ #35 Hardware name: System manufacturer System Product Name/ROG STRIX X570-E GAMING WIFI II, BIOS 4204 02/24/2022 Workqueue: events_unbound async_run_entry_fn v2: drop extra memcpy Fixes: 88c61827cedc ("drm/amd/display: dynamically allocate dml2_configuration_options structures") Reviewed-by: Harry Wentland <[email protected]> Tested-by: George Zhang <[email protected]> (v1) Suggested-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: George Zhang <[email protected]> Cc: Arnd Bergmann <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected]
2024-06-05drm/amd/display: Add UCLK p-state support message to dcn401Dillon Varone1-0/+4
[WHY&HOW] Improves on the SMU interface to explicitly declare P-State support. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-05drm/amd/display: Move fpo_in_use to stream_statusAlvin Lee1-1/+7
[Description] Refactor code and move fpo_in_use into stream_status to avoid unexpected changes to previous dc_state (i.e., current_state). Since stream pointers are shared between current and new dc_states, updating parameters of one stream will update the other as well which causes unexpected behaviors (i.e., checking that fpo_in_use isn't set in previous state and set in the new state is invalid). To avoid incorrect updates to current_state, move the fpo_in_use flag into dc_stream_status since stream_status is owned by dc and are not shared between different dc_states. Reviewed-by: Samson Tam <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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