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2024-09-18drm/amd/display: Restructure dpia link trainingPeichen Huang6-50/+181
[WHY] We intend to consolidate dp tunneling and conventional dp link training. [HOW] 1. Use the same link training entry for both dp and dpia 2. Move SET_CONFIG of non-transparent mode to dmub side 3. Add set_tps_notification dmub_cmd to notify tps request for non-transparent dpia link training 4. Check dpcd request result and abort link training early if dpia aux tunneling fails 5. Add option to avoid affect old product 6. Separately handle wait_time_microsec for dpia Reviewed-by: Cruise Hung <[email protected]> Reviewed-by: George Shen <[email protected]> Reviewed-by: Meenakshikumar Somasundaram <[email protected]> Signed-off-by: Peichen Huang <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-09-18drm/amd/display: Implement new DPCD register handlingRyan Seto2-0/+12
[WHY] There are some monitor timings that seem to be supported without DSC but actually require DSC to be displayed. A VESA SCR introduced a new max uncompressed pixel rate cap register that we can use to handle these edge cases. [HOW] SST: Read caps from link and invalidate timings that exceed the max limit but do not support DSC. Then check for options override when determining BPP. MST: Read caps from virtual DPCD peer device or daisy chained SST monitor and set validation set BPPs to max if pixel rate exceeds uncompressed limit. Validation set optimization continues as normal. Reviewed-by: Wenjing Liu <[email protected]> Signed-off-by: Ryan Seto <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-08-20drm/amd/display: fix double free issue during amdgpu module unloadTim Huang1-1/+1
Flexible endpoints use DIGs from available inflexible endpoints, so only the encoders of inflexible links need to be freed. Otherwise, a double free issue may occur when unloading the amdgpu module. [ 279.190523] RIP: 0010:__slab_free+0x152/0x2f0 [ 279.190577] Call Trace: [ 279.190580] <TASK> [ 279.190582] ? show_regs+0x69/0x80 [ 279.190590] ? die+0x3b/0x90 [ 279.190595] ? do_trap+0xc8/0xe0 [ 279.190601] ? do_error_trap+0x73/0xa0 [ 279.190605] ? __slab_free+0x152/0x2f0 [ 279.190609] ? exc_invalid_op+0x56/0x70 [ 279.190616] ? __slab_free+0x152/0x2f0 [ 279.190642] ? asm_exc_invalid_op+0x1f/0x30 [ 279.190648] ? dcn10_link_encoder_destroy+0x19/0x30 [amdgpu] [ 279.191096] ? __slab_free+0x152/0x2f0 [ 279.191102] ? dcn10_link_encoder_destroy+0x19/0x30 [amdgpu] [ 279.191469] kfree+0x260/0x2b0 [ 279.191474] dcn10_link_encoder_destroy+0x19/0x30 [amdgpu] [ 279.191821] link_destroy+0xd7/0x130 [amdgpu] [ 279.192248] dc_destruct+0x90/0x270 [amdgpu] [ 279.192666] dc_destroy+0x19/0x40 [amdgpu] [ 279.193020] amdgpu_dm_fini+0x16e/0x200 [amdgpu] [ 279.193432] dm_hw_fini+0x26/0x40 [amdgpu] [ 279.193795] amdgpu_device_fini_hw+0x24c/0x400 [amdgpu] [ 279.194108] amdgpu_driver_unload_kms+0x4f/0x70 [amdgpu] [ 279.194436] amdgpu_pci_remove+0x40/0x80 [amdgpu] [ 279.194632] pci_device_remove+0x3a/0xa0 [ 279.194638] device_remove+0x40/0x70 [ 279.194642] device_release_driver_internal+0x1ad/0x210 [ 279.194647] driver_detach+0x4e/0xa0 [ 279.194650] bus_remove_driver+0x6f/0xf0 [ 279.194653] driver_unregister+0x33/0x60 [ 279.194657] pci_unregister_driver+0x44/0x90 [ 279.194662] amdgpu_exit+0x19/0x1f0 [amdgpu] [ 279.194939] __do_sys_delete_module.isra.0+0x198/0x2f0 [ 279.194946] __x64_sys_delete_module+0x16/0x20 [ 279.194950] do_syscall_64+0x58/0x120 [ 279.194954] entry_SYSCALL_64_after_hwframe+0x6e/0x76 [ 279.194980] </TASK> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Tim Huang <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-08-20drm/amd/display: Fix construct_phy with MXM connectorIlya Bakoulin1-0/+1
[Why/How] The call to construct_phy will fail in cases where connector type is MXM, and the dc_link won't be properly created/initialized. Reviewed-by: Wenjing Liu <[email protected]> Signed-off-by: Ilya Bakoulin <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-08-20drm/amd/display: Support UHBR10 link rate on eDPSung Joon Kim2-2/+5
[why] Supporting UHBR10 link rate on eDP leverages the existing DP2.0 code but need to add some small adjustments in code. [how] Acknowledge the given DPCD caps for UHBR10 link rate support and allow DP2.0 programming sequence and link training for eDP. Reviewed-by: Wenjing Liu <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-08-20drm/amd/display: Allow UHBR Interop With eDP Supported Link Rates TableMichael Strauss4-35/+40
[WHY] eDP 2.0 is introducing support for UHBR link rates, however current eDP ILR link optimization does not account for UHBR capabilities. Either UHBR capabilities will be provided via the same 128b/132b rate DPCD caps that are currently used on DP2.1, or Table 4-13 may be updated to include UHBR rates. [HOW] Add extra Supported Link Rates table translations for UHBR10/13.5/20. Update eDP link setting optimization search to be aware of 128b/132b DPCD rate caps in order to unblock UHBR on panels with Supported Link Rates table. Reviewed-by: Wenjing Liu <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-08-20drm/amd/display: Update HPO I/O When Handling Link Retrain Automation RequestMichael Strauss1-0/+8
[WHY] Previous multi-display HPO fix moved where HPO I/O enable/disable is performed. The codepath now taken to enable/disable HPO I/O is not used for compliance test automation, meaning that if a compliance box being driven at a DP1 rate requests retrain at UHBR, HPO I/O will remain off if it was previously off. [HOW] Explicitly update HPO I/O after allocating encoders for test request. Reviewed-by: Charlene Liu <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-08-06drm/amd/display: Revert Avoid overflow assignmentGabe Teeger1-2/+1
This reverts commit a15268787b79 ("drm/amd/display: Avoid overflow assignment in link_dp_cts") Due to regression causing DPMS hang. Reviewed-by: Alex Hung <[email protected]> Signed-off-by: Gabe Teeger <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-08-06drm/amd/display: Print Pcon FRL Link BW in Debug MessageFangzhi Zuo1-0/+2
Under autonomous mode, source reads dpcd DP_PCON_HDMI_POST_FRL_STATUS for the frl link status. Without dsc passthrough, it serves as bw bottleneck on the entire link, compared with the dp link from source to the converter where dsc is available. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Fangzhi Zuo <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-27drm/amd/display: Avoid overflow assignment in link_dp_ctsAlex Hung1-1/+2
sampling_rate is an uint8_t but is assigned an unsigned int, and thus it can overflow. As a result, sampling_rate is changed to uint32_t. Similarly, LINK_QUAL_PATTERN_SET has a size of 2 bits, and it should only be assigned to a value less or equal than 4. This fixes 2 INTEGER_OVERFLOW issues reported by Coverity. Signed-off-by: Alex Hung <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Check link_res->hpo_dp_link_enc before using itAlex Hung1-0/+5
[WHAT & HOW] Functions dp_enable_link_phy and dp_disable_link_phy can pass link_res without initializing hpo_dp_link_enc and it is necessary to check for null before dereferencing. This fixes 1 FORWARD_NULL issue reported by Coverity. Fixes: 0beca868cde8 ("drm/amd/display: Check link_res->hpo_dp_link_enc before using it") Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Check null pointers before multiple usesAlex Hung2-2/+8
[WHAT & HOW] Poniters, such as stream_enc and dc->bw_vbios, are null checked previously in the same function, so Coverity warns "implies that stream_enc and dc->bw_vbios might be null". They are used multiple times in the subsequent code and need to be checked. This fixes 10 FORWARD_NULL issues reported by Coverity. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Check null pointers before usedAlex Hung1-1/+1
[WHAT & HOW] Poniters, such as dc->clk_mgr, are null checked previously in the same function, so Coverity warns "implies that "dc->clk_mgr" might be null". As a result, these pointers need to be checked when used again. This fixes 10 FORWARD_NULL issues reported by Coverity. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Check link_res->hpo_dp_link_enc before using itAlex Hung1-0/+7
[WHAT & HOW] Functions dp_enable_link_phy and dp_disable_link_phy can pass link_res without initializing hpo_dp_link_enc and it is necessary to check for null before dereferencing. This fixes 2 FORWARD_NULL issues reported by Coverity. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Fix DP-DVI dongle hotplugGabe Teeger1-4/+1
[why] Hotplugging with a DVI-DP dongle on pre-rdna embedded platform working about half the time. The regression was found to be the setting of link->type here. [what] Reverts fix besides the logging added. Reviewed-by: Wenjing Liu <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Gabe Teeger <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: fix dscclk programming sequence on DCN401Wenjing Liu1-14/+27
[why] The mux to switch between refclk and dto_dsc_clk is non double buffered. However dto dsc clk's phase and modulo divider registers are currently configured as double buffered update. This causes a problem when we switch to use dto dsc clk and program phase and modulo in the same sequence. In this sequence dsc clk is switched to dto but the clock divider programming doesn't take effect until next frame. When we try to program DSCC registers, SMN bus will hang because dto dsc clk divider phase is set to 0. [how] Configure phase and modulo to take effect immediately. Always switch to dto dsc clk before DSC clock is unagted. Switch back to refclk after DSC clock is gated. Acked-by: Rodrigo Siqueira <[email protected]> Reviewed-by: Jerry Zuo <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Replace assert with error message in dp_retrieve_lttpr_cap()Roman Li1-1/+5
[Why] When assert in dp_retrieve_lttpr_cap() is hit, dmesg has traces like: RIP: 0010:dp_retrieve_lttpr_cap+0xcc/0x1a0 [amdgpu] Call Trace: <TASK> dp_retrieve_lttpr_cap+0xcc/0x1a0 [amdgpu] report_bug+0x1e8/0x240 handle_bug+0x46/0x80 link_detect+0x35/0x580 [amdgpu] It happens when LTTPRs fail to increment dpcd repeater count. We have a recovery action in place for such cases. Assert is misleading, an indicative error in dmesg is more useful. [How] Remove ASSERT and use DC_LOG_ERROR instead. Reviewed-by: Michael Strauss <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-16drm/amd/display: Move DIO documentation to the right placeRodrigo Siqueira2-9/+29
When building the kernel-doc, it complains with the below warning: ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h:1: warning: no structured comments found ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h:1: warning: no structured comments found This warning was caused by the wrong use of the ':export:' and the lack of function documentation in the file pointed under the ':internal:'. This commit addresses those issues by relocating the overview documentation to the correct C file, removing the ':export:' options, and adding two simple kernel-doc to ensure that ':internal:' does not have any warning. Cc: Alex Deucher <[email protected]> Acked-by: Alex Deucher <[email protected]> Reported-by: Stephen Rothwell <[email protected]> Link: https://lore.kernel.org/dri-devel/[email protected]/ Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-01drm/amd/display: Fix possible overflow in integer multiplicationAlex Hung1-1/+1
[WHAT & HOW] Integer multiplies integer may overflow in context that expects an expression of unsigned/siged long long (64 bits). This can be fixed by casting integer to unsigned/siged long long to force 64 bits results. This fixes 26 OVERFLOW_BEFORE_WIDEN issues reported by Coverity. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-27drm/amd/display: Validate function returnsAlex Hung1-2/+1
[WHAT & HOW] Function return values must be checked before data can be used in subsequent functions. This fixes 4 CHECKED_RETURN issues reported by Coverity. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-27drm/amd/display: Fix reduced resolution and refresh rateDaniel Sa1-10/+11
[WHY] Some monitors are forced to a lower resolution and refresh rate after system restarts. [HOW] Some monitors may give invalid LTTPR information when queried such as indicating they have one DP lane instead of 4. If given an invalid DPCD version, skip over getting lttpr link rate and lane counts. Reviewed-by: Wenjing Liu <[email protected]> Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Daniel Sa <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-27drm/amd/display: Run DC_LOG_DC after checking link->link_encAlex Hung1-3/+3
[WHAT] The DC_LOG_DC should be run after link->link_enc is checked, not before. This fixes 1 REVERSE_INULL issue reported by Coverity. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-27drm/amd/display: Remove redundant checks for pipe_ctx->streamAlex Hung1-1/+1
[WHAT & HOW] The null checks for pipe_ctx->stream and pipe_ctx->stream_res.tg are redundant as they were already dereferenced previously, as reported by Coverity; therefore the null checks are removed. This fixes 6 REVERSE_INULL issues reported by Coverity. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-27drm/amd/display: Send DP_TOTAL_LTTPR_CNT during detection if LTTPR is presentMichael Strauss1-1/+9
[WHY] New register field added in DP2.1 SCR, needed for auxless ALPM [HOW] Echo value read from 0xF0007 back to sink Reviewed-by: Wenjing Liu <[email protected]> Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14Revert "drm/amd/display: workaround for oled eDP not lighting up on DCN401"Joshua Aberback1-3/+0
This reverts commit e902dd7f3e3b93a401e1d3c0322cce933e75e809. A proper fix for this issue has been implemented in DMUB FW. So, no need to keep the workaround. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Joshua Aberback <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Remove reduntant comparisons by CoverityIvan Lipski1-2/+6
[WHY] Coverity analysis of the Upstream display driver code (amd-staging-drm-next) flagged these three functions as containing 'CONSTANT_EXPRESSION_RESULT' errors, i. e. the conditionals are reduntant since their result is predetermined. fixpt31_32.c: The two flagged 'ASSERT' lines redundant since they are always true: - LONG_MAX equals to the largest 'signed long long' number - res.value is type 'signed long long', So, the condition inside the 'ASSERTS's is always link_dp_training.c: The flagged conditional statement is always false: - 'max_requested.FFE_PRESET.settings.level' is 4 bits, so its max possible value is 15 - 'DP_FFE_PRESET_MAX_LEVEL' equals to 15. So, the conditional statement is always false and the wrapped code never executes. [HOW] Removed lines flagged by Coverity analysis. Reviewed-by: Sun peng Li <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14Revert "drm/amd/display: Handle HPD_IRQ for internal link"Sung-huai Wang1-15/+9
[How&Why] This reverts commit 239b31bd5c3fef3698440bf6436b2068c6bb08a3. Due to the it effects Replay resync. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Sung-huai Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: use preferred link settings for dp signal onlyWenjing Liu1-14/+10
[why] We set preferred link settings for virtual signal. However we don't support virtual signal for UHBR link rate. If preferred is set to UHBR link rate, we will allow virtual signal with UHBR link rate which causes system crashes. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Ignore UHBR13.5 cable ID cap for passive cable max link rateGeorge Shen1-1/+2
[Why] Passive DP40 cables were updated in the latest DP spec to support UHBR13.5 link rate. Current max link rate logic checks against the cable ID DPCD even for passive cables. [How] Ignore UHBR13.5 cable ID DPCD cap in get_max_link_rate logic. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: George Shen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Add fallback defaults for invalid LTTPR DPCD capsMichael Strauss1-3/+16
[WHY] Some sinks are observed to return invalid LTTPR revision and/or invalid LTTPR link rate capabilities. [HOW] Assume any LTTPR which reports invalid max link rate supports HBR3. Don't validate LTTPR DPCD revision in dp_is_lttpr_present check. Reviewed-by: George Shen <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Update FIXED_VS retimer training pattern delayMichael Strauss1-3/+3
[WHY] Needed for PHY patterns as well to perform electrical compliance. Also need to increase wait time from 30ms to 50ms to resolve very intermittent UHBR20 link training failures. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Program DIG FE source select for DVI before PHY enAlvin Lee1-1/+1
[Description] In newer DCN's the programming of SYMCLK_FE_SRC_SEL depends on the value of DIG_FE_SOURCE_SELECT. If DIG_FE_SOURCE_SELECT is not already programmed at the time of PHY / DIG enable then the FW sequence will program an incorrect SYMCLK source. Ensure that we program DIG_FE_SOURCE_SELECT for all DIO scenarios (DVI in this particular case) before going through the PHY / DIG enable sequence. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Extend PSRSU residency modeJack Chang2-3/+3
1. To support multiple PSRSU residency measurement mode Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Jack Chang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-05drm/amd/display: Add retires when read DPCDJoan Lee1-6/+20
[why & how] Sometimes read DPCD return fail while result not retrieved yet. Add retries mechanism in Replay handle hpd irq to get real result. Reviewed-by: Jerry Zuo <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Joan Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-05drm/amd/display: workaround for oled eDP not lighting up on DCN401Joshua Aberback1-0/+3
[Why] Currently there's an issue on DCN401 that prevents oled eDP panels from being lit up that is still under investigation. To unblock dev work while investigating, we can work around the issue by skipping toggling the enablement of the backlight. [How] - new debug bit that will skip touching backlight enable DPCD for oled Reviewed-by: Alvin Lee <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Joshua Aberback <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-05drm/amd/display: turn on symclk for dio virtual stream in dpms sequenceWenjing Liu3-16/+25
[why] In order to support glitchless display clock ramping for virtual stream, we must turn on symclk for stream encoder. The code will power on phy and enable symclk for dio encoder during virtual stream dpms sequence. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-23drm/amd/display: Refactor construct_phy function in dc/link/link_factory.cSrinivasan Shanmugam1-33/+34
This commit modifies the construct_phy function to handle the case where `bios->integrated_info` is NULL and to address a compiler warning about a large stack allocation. Upon examination, it was found that the local `integrated_info` structure was just used to copy values which is large and was being declared directly on the stack which could potentially lead to performance issues. This commit changes the code to use `bios->integrated_info` directly, which avoids the need for a large stack allocation. The function now checks if `bios->integrated_info` is NULL before entering a for loop that uses it. If `bios->integrated_info` is NULL, the function skips the for loop and continues executing the rest of the code. This ensures that the function behaves correctly when `bios->integrated_info` is NULL and improves compatibility with dGPUs. Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_factory.c: In function ‘construct_phy’: drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_factory.c:743:1: warning: the frame size of 1056 bytes is larger than 1024 bytes [-Wframe-larger-than=] Cc: Wenjing Liu <[email protected]> Cc: Jerry Zuo <[email protected]> Cc: Qingqing Zhuo <[email protected]> Cc: Tom Chung <[email protected]> Cc: Alvin Lee <[email protected]> Cc: Rodrigo Siqueira <[email protected]> Cc: Roman Li <[email protected]> Cc: Hersen Wu <[email protected]> Cc: Alex Hung <[email protected]> Cc: Aurabindo Pillai <[email protected]> Cc: Harry Wentland <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Suggested-by: Wenjing Liu <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-20drm/amd/display: remove unused struct 'aux_payloads'Dr. David Alan Gilbert1-4/+0
'aux_payloads' is unused since commit eae5ffa9bd7b ("drm/amd/display: Switch ddc to new aux interface") Remove it. Signed-off-by: Dr. David Alan Gilbert <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-20drm/amd/display: Not fallback if link BW is smaller than req BWCruise2-17/+4
[Why] When the link BW is smaller than the request BW, the DP LT just kept running and fallback to lower link config. DP LT just aborted if is_hpd_pending bit is high. But is_hpd_pending bit indicates a new HPD event received. It doesn't mean the HPD is low. [How] Abort the DP LT if the link BW is smaller than the request BW. Remove checking is_hpd_pending bit in DP LT. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Cruise <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-13drm/amd/display: Check UHBR13.5 cap when determining max link capGeorge Shen1-4/+18
[WHY] UHBR13.5 support is optional, even if UHBR20 is supported by the device. If source supports max UHBR13.5 while sink, cable and LTTPR support UHBR20 but not UHBR13.5, UHBR10 should be used as the max link cap. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: George Shen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-13drm/amd/display: Expand to higher link ratesSung Joon Kim1-0/+3
[WHY & HOW] To support higher link rates that sink allows, we need to make sure driver is ready and perform correct link-training sequence. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-08drm/amd/display: reset DSC clock in post unlock updateWenjing Liu1-2/+8
[why] Switching between DSC clock or disable DSC block are not double buffered update. Corruption is observed if these updates happen before DSC double buffered disconnection. [how] Move DSC disable and refclk reset to post unlock update. Wait for DSC double buffered disconnection and all mpccs are disconnected before reset DSC clock. Reviewed-by: Samson Tam <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-08drm/amd/display: Reset input mode for DIG on encoder resetDillon Varone1-0/+2
[WHY & HOW] Make enable and disable sequences symmetric. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-08drm/amd/display: Refactor input mode programming for DIG FIFODillon Varone1-0/+3
[WHY] Input mode for the DIG FIFO should be programmed as part of stream encoder setup. [HOW] Pre-calculate the pixels per cycle as part of the pixel clock params, and program as part of stream encoder setup. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amd/display: Fix Coverity INTEGER_OVERFLOW within ↵Hersen Wu1-1/+1
decide_fallback_link_setting_max_bw_policy [Why] For addtion (uint8_t) variable + constant 1, coverity generates message below: Truncation due to cast operation on "cur_idx + 1" from 32 to 8 bits. Then Coverity assume result is 32 bits value be saved into 8 bits variable. When result is used as index to access array, Coverity suspects index invalid. [How] Change varaible type to uint32_t. Reviewed-by: Alex Hung <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Hersen Wu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amd/display: Skip updating link encoder for unknown eng_idAlex Hung1-1/+1
This prevents accessing to negative index of link_encoders array. This fixes an OVERRUN issue reported by Coverity. Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amd/display: Add missing NULL pointer check within dpcd_extend_address_rangeHersen Wu1-0/+1
[Why & How] ASSERT if return NULL from kcalloc. Reviewed-by: Alex Hung <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Hersen Wu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amd/display: Check index for aux_rd_interval before usingAlex Hung1-2/+2
aux_rd_interval has size of 7 and should be checked. This fixes 3 OVERRUN and 1 INTEGER_OVERFLOW issues reported by Coverity. Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Change ASSR disable sequenceSwapnil Patel1-2/+1
[Why] Currently disabling ASSR before stream is disabled causes visible display corruption. [How] Move disable ASSR command to after stream has been disabled. Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Swapnil Patel <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Fix FEC_READY write on DP LTIlya Bakoulin1-8/+6
[Why/How] We can miss writing FEC_READY in some cases before LT start, which violates DP spec. Remove the condition guarding the DPCD write so that the write happens unconditionally. Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Ilya Bakoulin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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