| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2024-09-18 | drm/amd/display: Clear cached watermark after resume | Charlene Liu | 1 | -0/+1 | |
| [WHY] Driver could skip program watermarks when resume from S0i3/S4. [HOW] Clear the cached one first to make sure new value gets applied. Reviewed-by: Alvin Lee <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-08-13 | drm/amd/display: Unlock Pipes Based On DET Allocation | Austin Zheng | 1 | -0/+23 | |
| [Why] DML21 does not allocate DET evenly between pipes. May result in underflow when unlocking the pipes as DET could be overallocated. [How] 1. Unlock pipes that have a decreased amount of DET allocation 2. Wait for the double buffer to be updated. 3. Unlock the remaining pipes. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Austin Zheng <[email protected]> Signed-off-by: Tom Chung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-07-23 | drm/amd/display: rename dcn3/dcn4 to more sound terms | Aurabindo Pillai | 1 | -182/+182 | |
| Use more accurate names to refer to the asic architecture. dcn3 in DML actually refers to DCN32 and DCN321, so rename it to dcn32x dcn4 refers to any DCN4x soc., and hence rename dcn4 to dcn4x Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-07-01 | drm/amd/display: Add ASIC cap to limit DCC surface width | George Shen | 1 | -0/+6 | |
| [Why] Certain configurations of DCN401 require ODM4:1 to support DCC for 10K surfaces. DCC should be conservatively disabled in those cases. The issue is that current logic limits 10K surface DCC for all configurations of DCN401. [How] Add DC ASIC cap to indicate max surface width that can support DCC. Disable DCC if this ASIC cap is non-zero and surface width exceeds it. Reviewed-by: Jun Lei <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: George Shen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-06-27 | drm/amd/display: Enable DCC on DCN401 | Aurabindo Pillai | 4 | -0/+291 | |
| [WHAT] Add registers and entry points to enable DCC on DCN4x Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-06-27 | drm/amd/display: Validate function returns | Alex Hung | 1 | -1/+2 | |
| [WHAT & HOW] Function return values must be checked before data can be used in subsequent functions. This fixes 4 CHECKED_RETURN issues reported by Coverity. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-06-05 | drm/amd/display: Support new VA page table block size | Chris Park | 1 | -3/+24 | |
| [Why] Page table definition increased up to 2MB. [How] Define new use case of page table for VA. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Chris Park <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-05-29 | drm/amd/display: Remove unused code | Rodrigo Siqueira | 1 | -5/+1 | |
| This commit removes some unused code with the required adjustments. Signed-off-by: Rodrigo Siqueira <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-05-20 | drm/amd/display: Refactor HUBBUB into component folder for DCN401 | Harikrishna Revalla | 3 | -1/+1130 | |
| [why] Cleaning up the code refactor requires hubbub to be in its own component. [how] Move all DCN401 files under newly created hubbub folder and fixing the makefiles. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Harikrishna Revalla <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-30 | drm/amd/display: Refactor HUBBUB into component folder | Revalla Hari Krishna | 19 | -0/+7372 | |
| [why] cleaning up the code refactor requires hubbub to be in its own component. [how] Move all files under newly created hubbub folder and fix the makefiles. Reviewed-by: Martin Leung <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Revalla Hari Krishna <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||