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path: root/drivers/gpu/drm/amd/display/dc/dsc
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2024-09-18drm/amd/display: Add HDMI DSC native YCbCr422 supportLeo Ma1-2/+3
[WHY && HOW] For some HDMI OVT timing, YCbCr422 encoding fails at the DSC bandwidth check. The root cause is our DSC policy for timing doesn't account for HDMI YCbCr422 native support. Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Reviewed-by: Chris Park <[email protected]> Signed-off-by: Leo Ma <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-09-18drm/amd/display: Implement new DPCD register handlingRyan Seto1-5/+5
[WHY] There are some monitor timings that seem to be supported without DSC but actually require DSC to be displayed. A VESA SCR introduced a new max uncompressed pixel rate cap register that we can use to handle these edge cases. [HOW] SST: Read caps from link and invalidate timings that exceed the max limit but do not support DSC. Then check for options override when determining BPP. MST: Read caps from virtual DPCD peer device or daisy chained SST monitor and set validation set BPPs to max if pixel rate exceeds uncompressed limit. Validation set optimization continues as normal. Reviewed-by: Wenjing Liu <[email protected]> Signed-off-by: Ryan Seto <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-08-23drm/amd/display: Make dcn401_dsc_funcs staticJinjie Ruan1-1/+1
The sparse tool complains as follows: drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dcn401/dcn401_dsc.c:30:24: warning: symbol 'dcn401_dsc_funcs' was not declared. Should it be static? This symbol is not used outside of dcn401_dsc.c, so marks it static. Signed-off-by: Jinjie Ruan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-27drm/amd/display: Adjust reg field for DSC wait for disconnectRyan Seto3-3/+6
[WHY] DSC was waiting for the wrong field to disconnect cleanly. [HOW] Changed field the DSC disconnect was waiting on. Reviewed-by: Wenjing Liu <[email protected]> Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Ryan Seto <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-27drm/amd/display: Reset DSC memory statusDuncan Ma3-20/+71
[WHY] When system exits idle state followed by enabling the display, DSC memory may still be forced in a deep sleep or shutdown state. Intermittent DSC corruption is seen when display is visible. [HOW] When DSC is enabled, reset dsc memory to force and disable status. Reviewed-by: Nicholas Kazlauskas <[email protected]> Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Duncan Ma <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-29drm/amd/display: Remove unused codeRodrigo Siqueira1-5/+0
This commit removes some unused code with the required adjustments. Signed-off-by: Rodrigo Siqueira <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-20drm/amd/display: Fix POWERPC_64 compilationRoman Li1-1/+1
[Why] Compilation errors while compiling without CONFIG_DRM_AMD_DC_FP: "undefined reference to `dc_bandwidth_in_kbps_from_timing'" [How] Fix Makefile to move dsc files out of DC_FP guard. Fixes: 00c391102abc ("drm/amd/display: Add misc DC changes for DCN401") Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-20drm/amd/display: Move DSC functions from dc.c to dc_dsc.cWenjing Liu1-0/+96
Move dsc functions from dc.c to dc_dsc.c. Co-developed-by: George Shen <[email protected]> Signed-off-by: George Shen <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-13drm/amd/display: Allow higher DSC slice support for small timings on dcn401Wenjing Liu1-373/+39
[WHY] DML2.1 has added the support to determine ODM combine based on DSC slice count limitation. This support would allow us to support DSC slice higher than 4 on small timings. The change will allow higher DSC slice support independent from pixel clock in use. [HOW] Add a DCN401 get_enc_caps function to allow the support for DSC slice count higher than 4. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-08drm/amd/display: reset DSC clock in post unlock updateWenjing Liu4-14/+25
[why] Switching between DSC clock or disable DSC block are not double buffered update. Corruption is observed if these updates happen before DSC double buffered disconnection. [how] Move DSC disable and refclk reset to post unlock update. Wait for DSC double buffered disconnection and all mpccs are disconnected before reset DSC clock. Reviewed-by: Samson Tam <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amd/display: Fix invalid Copyright noticeLeo Ma1-2/+1
[Why && How] Copyright notice failed in the Palamida scan and make changes to align with our guidelines. Acked-by: Tom Chung <[email protected]> Signed-off-by: Leo Ma <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: take ODM slice count into account when deciding DSC sliceWenjing Liu1-7/+23
[why] DSC slice must be divisible by ODM slice count. [how] If DSC slice count is not a multiple of ODM slice count, increase DSC slice until it is. Otherwise fail to compute DSC configuration. Reviewed-by: Chaitanya Dhere <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-26drm/amd/display: Add misc DC changes for DCN401Aurabindo Pillai2-98/+12
Add miscellaneous changes to enable DCN401 init Signed-off-by: Aurabindo Pillai <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-26drm/amd/display: Add some DCN401 reg name to macro definitionsAurabindo Pillai1-0/+11
Update macros to cover DCN 4.0.1. Signed-off-by: Aurabindo Pillai <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-26drm/amd/display: Add new DCN401 sourcesAurabindo Pillai2-0/+1084
Add initial support for DCN 4.0.1. Signed-off-by: Aurabindo Pillai <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-26drm/amd/display: Fix division by zero in setup_dsc_configJose Fernandez1-1/+6
When slice_height is 0, the division by slice_height in the calculation of the number of slices will cause a division by zero driver crash. This leaves the kernel in a state that requires a reboot. This patch adds a check to avoid the division by zero. The stack trace below is for the 6.8.4 Kernel. I reproduced the issue on a Z16 Gen 2 Lenovo Thinkpad with a Apple Studio Display monitor connected via Thunderbolt. The amdgpu driver crashed with this exception when I rebooted the system with the monitor connected. kernel: ? die (arch/x86/kernel/dumpstack.c:421 arch/x86/kernel/dumpstack.c:434 arch/x86/kernel/dumpstack.c:447) kernel: ? do_trap (arch/x86/kernel/traps.c:113 arch/x86/kernel/traps.c:154) kernel: ? setup_dsc_config (drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.c:1053) amdgpu kernel: ? do_error_trap (./arch/x86/include/asm/traps.h:58 arch/x86/kernel/traps.c:175) kernel: ? setup_dsc_config (drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.c:1053) amdgpu kernel: ? exc_divide_error (arch/x86/kernel/traps.c:194 (discriminator 2)) kernel: ? setup_dsc_config (drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.c:1053) amdgpu kernel: ? asm_exc_divide_error (./arch/x86/include/asm/idtentry.h:548) kernel: ? setup_dsc_config (drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.c:1053) amdgpu kernel: dc_dsc_compute_config (drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.c:1109) amdgpu After applying this patch, the driver no longer crashes when the monitor is connected and the system is rebooted. I believe this is the same issue reported for 3113. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Jose Fernandez <[email protected]> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3113 Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: Update DSC compute parameter calculationRodrigo Siqueira1-4/+3
Adjust bytes per pixel calculation to use div_u64. Signed-off-by: Rodrigo Siqueira <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: Fix compiler warnings on high compiler warning levelsAric Cyr1-4/+4
[why] Enabling higher compiler warning levels results in many issues that can be trivially resolved as well as some potentially critical issues. [how] Fix all compiler warnings found with various compilers and higher warning levels. Primarily, potentially uninitialized variables and unreachable code. Reviewed-by: Leo Li <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-22drm/amd/display: Fix timing bandwidth calculation for HDMILeo (Hanghong) Ma1-0/+5
[Why && How] The current bandwidth calculation for timing doesn't account for certain HDMI modes overhead which leads to DSC can't be enabled. Add support to calculate the actual bandwidth for these HDMI modes. Reviewed-by: Chris Park <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Leo (Hanghong) Ma <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amd/display: Add DSC granular throughput adjustmentIlya Bakoulin1-2/+8
[Why/How] Update DSC DPCD parsing to take granular throughput adjustment into consideration. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Ilya Bakoulin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amd/display: Refactor DSC into component folderBhuvana Chandra Pinninti6-0/+1626
[why] To refactor DSC and make DSC files unit testable. [how] moved the dcnxx_dsc.c and .h files into corresponding dcn folders inside the dsc and cleared the linkage errors. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Bhuvana Chandra Pinninti <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-07drm/amd/display: Allow 16 max_slices for DP2 DSCFangzhi Zuo1-0/+11
Enable 12 and 16 max_slices for DP2 DSC Reviewed-by: Alvin Lee <[email protected]> Acked-by: Hersen Wu <[email protected]> Signed-off-by: Fangzhi Zuo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-18drm/amd/display: Add link encoding to timing BW calculation parametersGeorge Shen1-6/+18
[Why] There certain cases where the timing BW is dependent on the type of link encoding in use. Thus to calculate the correct BW required for a given timing, the link encoding should be added as a parameter. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: George Shen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-18drm/amd/display: Add stream overhead in BW calculations for 128b/132bGeorge Shen1-0/+42
[Why] Current BW calculations do not account for the additional padding added for uncompressed pixel-to-symbol packing. This results in X.Y being too low for 128b/132b SST streams in certain scenarios. If X.Y is too low, end user can observe image corruption. [How] Add function to calculate stream overhead to timing BW calculation for 128b/132b SST cases. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: George Shen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amd/display: drop redundant memset() in get_available_dsc_slices()Hamza Mahfooz1-2/+0
get_available_dsc_slices() returns the number of indices set, and all of the users of get_available_dsc_slices() don't cross the returned bound when iterating over available_slices[]. So, the memset() in get_available_dsc_slices() is redundant and can be dropped. Fixes: 97bda0322b8a ("drm/amd/display: Add DSC support for Navi (v2)") Reported-by: Christophe JAILLET <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-18drm/amd/display: DSC policy override when ODM combine is forcedNasir Osman1-1/+9
[why] When we force ODM combine with DSC, we lose several 8 bit and 10 bit modes in validation and thus not able to use HDR. This is due to the number of horizontal slices used in DSC not properly being accounted for currently when 2:1 ODM Combine is forced. [how] Enforce at least two horizontal slices are used for DSC when ODM combine is forced. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Nasir Osman <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-14drm/amd/display: convert link.h functions to function pointer styleWenjing Liu1-0/+53
[Why & How] All dc subcomponents should call another dc component via function pointers stored in a component structure. This is part of dc coding convention since the beginning. The reason behind this is to improve encapsulation and polymorphism. The function contract is extracted into a single link service structure defined in link.h header file and implemented only in link_factory.c instead of spreading across multiple files in link component file structure. Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: Rename DCN config to FPHarry Wentland1-1/+1
[Why & How] The only reason we have the DCN config is for floating point support. Rename it to make that clear and (hopefully) avoid misuse of the config in the future. Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: Build DSC without DCN configHarry Wentland1-0/+2
[Why & How] DSC needs DCN but we are trying reduce the usage of the DCN flag. It's easier to build the DSC code sprinkled around DC core and the DMs and just guard the place where DSC uses floating point code. Since DSC is never enabled on non-DCN ASICs this won't have any effect. Reviewed-by: Hamza Mahfooz <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: fix typo in dc_dsc_config_options structureMike Hsieh1-3/+3
[WHY] There is a typo in dc_dsc_config_options structure [HOW] Fix the typo Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Mike Hsieh <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: Add height granularity limitation for dsc slice height ↵Mike Hsieh1-12/+21
calculation [WHY] eDP add new limitation for Y granularity for selected update feature. DSC does not include this limitation while calculating slice height. [HOW] Add new limitation while looking for DSC slice height. Reviewed-by: Cruise Hung <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Mike Hsieh <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-31drm/amd/display: add rc_params_override option in dc_dsc_configWenjing Liu2-6/+9
[why] Current RC params are based on VESA recommended configurations. Some DSC sink may prefer non standard rc params values due to hardware limitations. To support those DSC sink we will allow DM to optionally pass rc_params_ovrd in dc_dsc_config so DC will override the default VESA recommended configurations. Reviewed-by: Martin Leung <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-03drm/amd: Fix spelling typo in commentspengfuyuan1-2/+2
Fix spelling typo in comments. Reported-by: k2ci <[email protected]> Signed-off-by: pengfuyuan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-04-25drm/display: Move DSC header and helpers into display-helper moduleThomas Zimmermann3-4/+4
DSC is the Display Stream Compression standard for DisplayPort. Move the DSC code into display/ and split the header into files for protocol core and DRM helpers. Adapt all users of the code. No functional changes. To avoid the proliferation of Kconfig options, DSC is part of DRM's support for DisplayPort. If necessary, a new option could make DSC an independent feature. Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Javier Martinez Canillas <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-04-25drm: Rename dp/ to display/Thomas Zimmermann1-1/+1
Rename dp/ to display/ to account for additional display-related helpers, such as HDMI. Update all related include statements. No functional changes. Various drivers, such as i915 and amdgpu, use similar naming scheme by putting code for video-output standards into a local display/ directory. The new directory's name is aligned with this convention. v2: * update commit message (Javier) Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Reviewed-by: Javier Martinez Canillas <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-04-06drm/amd/display: Correct Slice reset calculationChris Park1-2/+2
[Why] Once DSC slice cannot fit pixel clock, we incorrectly reset min slices to 0 and allow max slice to operate, even when max slice itself cannot fit the pixel clock properly. [How] Change the sequence such that we correctly determine DSC is not possible when both min slices and max slices cannot fit pixel clock per slice. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Chris Park <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-01-17drm/dp: Move public DisplayPort headers into dp/Thomas Zimmermann1-1/+1
Move all public DisplayPort headers into dp/ and update users. No functional changes. v3: * rebased onto latest drm-tip Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Daniel Vetter <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-11-24drm/amd/display: fixed an error related to 4:2:0/4:2:2 DSCGuo, Bing3-31/+4
[Why] OPTC_BYTES_PER_PIXEL calculation for 4:2:2 and 4:2:0 could have error. [How] Change to use following formula: OPTC_DSC_BYTES_PER_PIXEL = ceiling((chunk size * 2^28) / slice width) v2: squash in 64 bit divide fix (Alex) Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Bing Guo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-11-22drm/amd/display: Enable DSC over eDPMikita Lipski1-0/+8
[why] - Adding a DM interface to enable DSC over eDP on Linux - DSC over eDP will allow to power savings by reducing the bandwidth required to support panel's modes - Apply link optimization algorithm to reduce link bandwidth when DSC is enabled [how] - Read eDP panel's DSC capabilities - Apply DSC policy on eDP panel based on its DSC capabilities - Enable DSC encoder's on the pipe - Enable DSC on panel's side by setting DSC_ENABLE DPCD register - Adding link optimization algorithm to reduce link rate or lane count based Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-11-17drm/amd/display: Fix Coverity IssuesChris Park1-1/+5
[Why] Coverity discovers holes in logic that needs to be addressed for improved code integrity. [How] Address issues found by coverity without changing the actual logic. Reviewed-by: Aric Cyr <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Chris Park <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: move FPU associated DSC code to DML folderQingqing Zhuo5-1042/+1
[Why & How] As part of the FPU isolation work documented in https://patchwork.freedesktop.org/series/93042/, isolate code that uses FPU in DSC to DML, where all FPU code should locate. This change does not refactor any functions but move code around. Cc: Christian König <[email protected]> Cc: Hersen Wu <[email protected]> Cc: Anson Jacob <[email protected]> Cc: Harry Wentland <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Agustin Gutierrez <[email protected]> Tested-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-09-14drm/amd/display: move bpp range decision in decide dsc bw range functionWenjing Liu1-62/+64
[why] Before get dsc bw range is used to compute DSC bw range based on the given fixed bpp min/max input. The new change will merge any specs, signal, timing specific bpp range decision into this function. So the function needs to make a decision with all aspects considered. Acked-by: Mikita Lipski <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: George Shen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-09-14drm/amd/display: expose dsc overhead bw in dc dsc headerWenjing Liu1-37/+32
[why] DM needs to know how much overhead is added to DSC as result of AMD internal DSC limitation. Acked-by: Mikita Lipski <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: George Shen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-07-28drm/amd/display: Fixed EdidUtility build errorsMark Morra1-165/+228
[HOW] Added #ifdefs and refactored various parts of dc to allow dc_link to be built by AMD EDID UTILITY [WHY] dc_dsc was refactored moving some of the code that AMD EDID UTILITY needed to dc_link, so now dc_link needs to be included by AMD EDID UTILITY Squash in DCN config fix (Alex) Reviewed-by: Leung Martin <[email protected]> Acked-by: Solomon Chiu <[email protected]> Signed-off-by: Mark Morra <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-10drm/amd/display: add dsc stream overhead for dp onlyWenjing Liu1-13/+28
[why] Based on hardware team recommendation this additional dsc overhead is only required for DP DSC. [how] Add a check for is_dp and only apply the overhead if this flag is set. Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: Chris Park <[email protected]> Acked-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-28drm/amd/display: take max dsc stream bandwidth overhead into accountWenjing Liu3-70/+88
[why] As hardware team suggested that we need to add a max dsc bw overhead into existing stream bandwidth when DSC is used. The formula as below: max_dsc_bw_overhead = v_addressable * slice_count * 256 bit * pixel clock / v_total / h_total effective stream bandwidth = pixel clock * bpp stream bandwidth = effective stream bandwidth + dsc stream overhead Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Acked-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/display: Add changes for dsc bpp in 16ths and unify bw calculationsDillon Varone1-71/+34
[Why?] Some code still expected bpp to be used in whole bits, not 16ths. dsc.c uses redundant function now found in dc to calculate stream bandwidth from timing. [How?] Fix code to work with 16ths instead of whole bits for dsc bpp. Refactor get_dsc_bandwidth to accept inputs in 16ths of a bit. Use dc function to calculate bandwidth from timing, and make dsc bw calculation a part of dsc.c. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Solomon Chiu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/display: revert support for DID2.0 dsc passthroughJun Lei1-18/+11
3x4K60 displays over MST with DSC enabled was not able to light up due to this patch. Signed-off-by: Jun Lei <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-02drm/amd/display: implement support for DID2.0 dsc passthroughJun Lei1-11/+18
[Why] Some panels contain active converters (e.g. DP to MIPI) which only support restricted DSC configurations. DID2.0 adds support for such displays to explicitly define per timing BPP restrictions on DSC. Ignoring these restrictions leads to blackscreen. [How] Add parsing in DID2.0 parser to get this bpp info. Add support in DSC module to constraint target bpp based on this info. Signed-off-by: Jun Lei <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu/display: drop DCN support for aarch64Alex Deucher1-4/+0
From Ard: "Simply disabling -mgeneral-regs-only left and right is risky, given that the standard AArch64 ABI permits the use of FP/SIMD registers anywhere, and GCC is known to use SIMD registers for spilling, and may invent other uses of the FP/SIMD register file that have nothing to do with the floating point code in question. Note that putting kernel_neon_begin() and kernel_neon_end() around the code that does use FP is not sufficient here, the problem is in all the other code that may be emitted with references to SIMD registers in it. So the only way to do this properly is to put all floating point code in a separate compilation unit, and only compile that unit with -mgeneral-regs-only." Disable support until the code can be properly refactored to support this properly on aarch64. Acked-by: Will Deacon <[email protected]> Reported-by: Ard Biesheuvel <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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