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2024-07-23drm/amd/display: Refactoring HPORevalla Hari Krishna5-1882/+1
[Why] To refactor HPO files [How] Moved hpo related files to specific hpo folder and update Makefiles. Reviewed-by: Martin Leung <[email protected]> Signed-off-by: Revalla Hari Krishna <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-01drm/amd/display: Move dio files into dio folderBhuvanachandra Pinninti3-972/+1
[why] Refactor the code of dio to unit test. [how] Moved files to respective folders and changed cMakeLists and makefiles. Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Bhuvanachandra Pinninti <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-27drm/amd/display: Fix Makefile copyright noticesAlex Deucher1-8/+2
Leftover copy pasta from original code. Reviewed-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2024-05-08drm/amd/display: Refactor HUBP into component folder.Bhuvana Chandra Pinninti3-370/+1
[why] cleaning up the code refactor requires hubp to be in its own component. [how] move all files under newly created hubp folder and fixing the makefiles. Reviewed-by: Martin Leung <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Bhuvana Chandra Pinninti <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-08drm/amd/display: Providing a mechanism to have a custom pwm frequencySreeja Golui2-0/+17
[Why] Providing a mechanism to manipulate the pwm frequency on the individual GPUs and monitor the transition during the switch. [How] Added a variable in dc_debug_options data structure. Using this variable to call the newly added command on the firmware. Reviewed-by: Harry Vanzylldejong <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Sreeja Golui <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amd/display: Refactor DCCG into component folderRevalla Hari Krishna3-995/+1
[why] cleaning up the code refactor requires dccg to be in its own component. [how] move all files under newly created dccg folder and fixing the makefiles. Reviewed-by: Martin Leung <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Revalla Hari Krishna <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Refactor HUBBUB into component folderRevalla Hari Krishna3-1238/+1
[why] cleaning up the code refactor requires hubbub to be in its own component. [how] Move all files under newly created hubbub folder and fix the makefiles. Reviewed-by: Martin Leung <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Revalla Hari Krishna <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-26drm/amd/display: Handle Y carry-over in VCP X.Y calculationGeorge Shen1-0/+6
Theoretically rare corner case where ceil(Y) results in rounding up to an integer. If this happens, the 1 should be carried over to the X value. CC: [email protected] Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: George Shen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-26drm/amd/display: Increase SAT_UPDATE_PENDING timeoutDmytro Laktyushkin1-1/+1
Headless dp 2.0 will take longer to update. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Dmytro Laktyushkin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-26drm/amd/display: Add some missing HDMI registers for DCN3xRodrigo Siqueira1-0/+6
This commit add some missing HDMI control registers to DCN3x. Signed-off-by: Rodrigo Siqueira <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-26drm/amd/display: Add missing debug registers for DCN2/3/3.1Rodrigo Siqueira1-0/+2
This commit add some missing debug registers for DPCS and RDPC debug. Signed-off-by: Rodrigo Siqueira <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: refactor vpg.hParandhaman K1-0/+1
why and how: as part of cleanup, need to refactor vpg. It was improperly referenced as a dcn specfic part of link. the dcn agnostic code needed was ripped out and put into vpg.h, now in dc/inc/hw. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Parandhaman K <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: Add option to configure mapping policy for edp0 on dp1Lewis Huang1-1/+8
[Why] We want flexibility to choose how pwrseq instance is mapped to eDP panel [How] Add configuration option to choose the pwrseq mapping policy. When enabled, allow fixed mapping between DIG inst to pwrseq inst. Reviewed-by: Anthony Koo <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Lewis Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: Add code comments clock and encode codeRodrigo Siqueira1-0/+4
This commit adds some comments to make easier to understand the clock update for DCN 201, the encode function, and other minor comments. Signed-off-by: Rodrigo Siqueira <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-03-27drm/amd/display: Modify DHCUB waterwark structures and functionsDillon Varone1-4/+4
[WHY&HOW] Converting the watermark set structure to a union and modifying some interfaces to accommodate future usage. Reviewed-by: Chaitanya Dhere <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-03-22drm/amd/display: change aux_init to apu versionCharlene Liu2-1/+3
[why] APU has different refclk as dGPU which is used for AUX_DPHY setup Reviewed-by: Chris Park <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-03-22drm/amd/display: Power on VPG memory unconditionally if offDillon Varone1-1/+6
[WHY&HOW] Even if memory lower power feature policy states that it is disabled, VPG memory should still be poweerd on if it is currently disabled when requested. Reviewed-by: Chris Park <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-02-22drm/amd/display: Only allow dig mapping to pwrseq in new asicLewis Huang1-1/+17
[Why] The old asic only have 1 pwrseq hw. We don't need to map the diginst to pwrseq inst in old asic. [How] 1. Only mapping dig to pwrseq for new asic. 2. Move mapping function into dcn specific panel control component Cc: Stable <[email protected]> # v6.6+ Cc: Mario Limonciello <[email protected]> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3122 Reviewed-by: Anthony Koo <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Lewis Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-03drm/amd/display: Refactor INIT into component folderRevalla3-191/+1
[why] Move all init files to hwss folder. [how] moved the dcnxx_init.c and .h files into inside the hwss and cleared the linkage errors. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Martin Leung <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Revalla <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-19drm/amd/display: Wake DMCUB before sending a commandNicholas Kazlauskas2-4/+4
[Why] We can hang in place trying to send commands when the DMCUB isn't powered on. [How] For functions that execute within a DC context or DC lock we can wrap the direct calls to dm_execute_dmub_cmd/list with code that exits idle power optimizations and reallows once we're done with the command submission on success. For DM direct submissions the DM will need to manage the enter/exit sequencing manually. We cannot invoke a DMCUB command directly within the DM execution helper or we can deadlock. Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Reviewed-by: Hansen Dsouza <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amd/display: Pass pwrseq inst for backlight and ABMLewis Huang1-2/+3
[Why] OTG inst and pwrseq inst mapping is not align therefore we cannot use otg_inst as pwrseq inst to get DCIO register. [How] 1. Pass the correct pwrseq instance to dmub when set abm pipe. 2. LVTMA control index change from panel_inst to pwrseq_inst. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Phil Hsieh <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Lewis Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amd/display: Refactor OPTC into component folderParandhaman K3-578/+1
[why] Move all optc files to unique folder optc. [how] creating optc repo in dc, and moved the dcnxx_optc.c and .h files into corresponding new folders inside the optc and cleared the linkage errors by adding relative paths in the Makefile.template. Reviewed-by: Martin Leung <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Parandhaman K <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-17drm/amd/display: Refactor resource into component directoryMounika Adhuri3-2316/+1
[WHY] Move all resource files to unique folder resource. [HOW] Created resource folder in dc, moved the dcnxx_resource.c and dcnxx_resource.h files into corresponding new folders inside the resource and made appropriate changes for compilation in Makefiles. Reviewed-by: Martin Leung <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Mounika Adhuri <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-26drm/amd/display: Fix copyright notice in DC codeStylon Wang1-1/+1
[Why & How] Fix incomplete copyright notice in DC code. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Stylon Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-26drm/amd/display: Set the DML2 attribute to false in all DCNs older than ↵Rodrigo Siqueira1-0/+1
version 3.5 When DML2 was introduced, it targeted only new DCN versions. For controlling which ASIC should use this new version of DML, it was introduced the using_dml2 attribute. To avoid ambiguities, this commit explicitly sets using_dml2 to false in all ASICs that do not support DML2. Cc: Vitaly Prosyak <[email protected]> Cc: Roman Li <[email protected]> Cc: Qingqing Zhuo <[email protected]> Cc: Daniel Wheeler <[email protected]> Cc: Alex Deucher <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-26drm/amd/display: reprogram det size while seamless bootHugo Hu1-0/+23
[Why] During system boot in second screen only mode on a seamless boot system, there is a chance that the pipe's det size might not be reset. [How] Reset the det size while resetting the pipe during seamless boot. Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Hugo Hu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Refactor HWSS into component folderMounika Adhuri5-667/+4
[why] Rename hw_sequencer to hwseq. Move all hwseq files to unique folder hwss. [how] creating hwss repo in dc, and moved the dcnxx_hwseq.c and .h files into corresponding new folders inside the hwss and cleared the linkage errors by adding relative paths in the Makefile.template. Reviewed-by: Martin Leung <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Mounika Adhuri <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-28drm/amd/display: Create one virtual connector in DCHarry Wentland1-1/+2
[WHAT] Prepare a virtual connector for writeback. Reviewed-by: Alex Hung <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amd/display: set stream gamut remap matrix to MPC for DCN3+Melissa Wen1-1/+1
dc->caps.color.mpc.gamut_remap says there is a post-blending color block for gamut remap matrix for DCN3 HW family and newer versions. However, those drivers still follow DCN10 programming that remap stream gamut_remap_matrix to DPP (pre-blending). To enable pre-blending and post-blending gamut_remap matrix supports at the same time, set stream gamut_remap to MPC and plane gamut_remap to DPP for DCN families that support both. It was tested using IGT KMS color tests for DRM CRTC CTM property and it preserves test results. Signed-off-by: Melissa Wen <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amd/display: switch DC over to the new DRM logging macrosHamza Mahfooz1-0/+2
For multi-GPU systems it is difficult to tell which GPU a particular message is being printed for and that is undesirable because it complicates debugging efforts. Also, the new macros allow us to enable logging for particular parts of the codebase more selectively (since we no longer need to throw everything at DRM_DEBUG_KMS()). So, for the reasons outlined above we should switch to the new macros. We can accomplish this by using the existing DC_LOGGER code to pass around the relevant `struct drm_device` which will be fed to the new macros in logger_types.h. Also, we must get rid of all instances of the DC_LOG_.*() functions that are currently in amdgpu_dm since we don't use the DC logger there and we can simply refer to the macros directly there instead. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Update DCN31 for DCN35 supportQingqing Zhuo3-2/+17
[Why & How] Update DCN31 files for DCN35 usage. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: correct z8_watermark 16bit to 20bit maskCharlene Liu1-16/+16
remove double adjustment for DPREFCLK SS. dprefclk adjusted with SS is used for dp audio only. if adjust DP_DTO, need to adjust VID_M/N Reviewed-by: Muhammad Ahmed <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: add more pipe resource interfacesWenjing Liu1-0/+1
Redesign pipe resource interfaces in resource.h file. The new interface design addresses the issue with lack of pipe topology encapsulation and lack of pipe accessors. Reviewed-by: Jun Lei <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: fix static screen detection settingSungHuai Wang1-1/+1
[WHY] OTG_STATIC_SCREEN_EVENT_MASK is changed in DCN3, but we still follow DCN2 to apply setting for OTG_STATIC_SCREEN_EVENT_MASK. [How] Add new function to apply correct settings for DCN3 series. Reviewed-by: Anthony Koo <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: SungHuai Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-15drm/amd/display: avoid crash and add z8_marks related in dmlCharlene Liu1-2/+2
[why] add dml1 used calculate_wm_and_dlg function pointer check to prevent crash. add z8 watermarks to struct for later asic use Reviewed-by: Alvin Lee <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-15drm/amd/display: disable clock gating logic reversed bug fixMuhammad Ahmed1-2/+2
[Why] disable clock gating logic reversed bug fix Reviewed-by: Charlene Liu <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Muhammad Ahmed <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-07drm/amd/display: rename acquire_idle_pipe_for_layer to ↵Wenjing Liu1-1/+1
acquire_free_pipe_as_sec_dpp_pipe [why] Secondary DPP pipes are used for rendering secondary layers of planes. The name "for layer" doesn't make it obvious. The function is acquiring a free pipe as secondary dpp pipe only. We rename it so it is more obvious. In a future follow up change, we want to add functions to acquire free pipe as opp head pipe or otg master pipe as well. They will have their separate allocation priority. Reviewed-by: Jun Lei <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-07drm/amd/display: Add Functions to enable Freesync Panel ReplayBhawanpreet Lakha1-0/+12
Add various functions for replay, such as construct, destroy, enable get_state, and copy_setting etc. These functions communicate with the firmware to setup and enable panel replay Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-07drm/amd/display: Add structs for Freesync Panel ReplayBhawanpreet Lakha1-0/+1
In some instances, the GPU is transmitting repeated frame to the sink without any updates or changes in the content. These repeat transmission are wasteful, resulting in power draw in different aspects of the system 1. DCN is fetching the frame of data from DF/UMC/DRAM. This memory traffic prevents power down of parts of this HW path. 2. GPU is transmitting pixel data to the display through the main link of the DisplayPort interface. This prevents power down of both the Source transmitter (TX) and the Sink receiver (RX)  The concepts of utilizing replay is similar to PSR, but there is a benefit of: Source and Sink remaining synchronized which allows for - lower latency when switching from replay to live frames - enable the possibility of more use cases - easy control of the sink's refresh rate during replay Due to Source and Sink remaining timing synchronized, Replay can be activated in more UI scenarios. Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Guard DCN31 PHYD32CLK logic against chip familyGeorge Shen1-1/+2
[Why] Current yellow carp B0 PHYD32CLK logic is incorrectly applied to other ASICs. [How] Add guard to check chip family is yellow carp before applying logic. Reviewed-by: Hansen Dsouza <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: George Shen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-18drm/amd/display: Fix DP2 link training failure with RCODaniel Miess2-20/+34
[Why] When RCO is enabled for symclk32_le we get failures during DP2 link traing compliance tests. [How] Break out symclk32_le RCO into a separate function that is called for hpo when link is enabled/disabled. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Daniel Miess <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-18drm/amd/display: Use is_dig_enable function instead of dcn10 hardcodeNicholas Kazlauskas1-1/+1
[Why] This can differ depending on ASIC and we can end up skipping all transmitter control if we're relying on the wrong bit as a shortcut for whether link is on/off. [How] The ASIC table itself provides the correct DIG check, use that instead of the dcn10 hardcode. Reviewed-by: Syed Hassan <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-07drm/amd/display: fix comment typoYueh-Shun Li1-1/+1
Spell "transmission" properly. Found by searching for keyword "tranm". Signed-off-by: Yueh-Shun Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-15drm/amd/display: Skip DPP DTO update if root clock is gatedNicholas Kazlauskas1-0/+8
[Why] Hardware implements root clock gating by utilizing the DPP DTO registers with a special case of DTO enabled, phase = 0, modulo = 1. This conflicts with our policy to always update the DPPDTO for cases where it's expected to be disabled. The pipes unexpectedly enter a higher power state than expected because of this programming flow. [How] Guard the upper layers of HWSS against this hardware quirk with programming the register with an internal state flag in DCCG. While technically acting as global state for the DCCG, HWSS shouldn't be expected to understand the hardware quirk for having DTO disabled causing more power than DTO enabled with this specific setting. This also prevents sequencing errors from occuring in the future if we have to program DPP DTO in multiple locations. Acked-by: Stylon Wang <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Jun Lei <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amd/display: Refactor fast update to use new HWSS build sequenceAlvin Lee1-0/+1
[Description] - Refactor HW sequencer to use a build / execute sequence - Also move gamma updates to become fast v2: squash in build fix ("drm/amd/display: Fix guarding of 'if (dc->debug.visual_confirm)'") Acked-by: Stylon Wang <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Reviewed-by: Jun Lei <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amd/display: remove unused definitionYang Li1-27/+0
Eliminate the following warnings: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_resource.c:1356:43: warning: unused variable 'res_create_maximus_funcs' drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_resource.c:894:38: warning: unused variable 'debug_defaults_diags' Reported-by: Abaci Robot <[email protected]> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5296 Fixes: 25879d7b4986 ("drm/amd/display: Clean FPGA code in dc") Signed-off-by: Yang Li <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amd/display: Clean FPGA code in dcQingqing Zhuo3-85/+42
[Why] Drop dead code for Linux. [How] Remove all IS_FPGA_MAXIMUS_DC and IS_DIAG_DC Reviewed-by: Ariel Bernstein <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amd/display: Add visual confirm color support for MCLK switchLeo (Hanghong) Ma1-1/+1
[Why && How] We would like to have visual confirm color support for MCLK switch. 1. Set visual confirm color to yellow: Vblank MCLK switch. 2. Set visual confirm color to cyan: FPO + Vblank MCLK switch. 3. Set visual confirm color to pink: Vactive MCLK switch. Reviewed-by: Jun Lei <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Leo (Hanghong) Ma <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-24drm/amd/display: add pixel rate based CRB allocation supportDmytro Laktyushkin1-0/+1
This feature is meant to unblock PSTATE for certain high end display configs on dcn315. This is achieved by allocating CRB to detile buffer based on display requirements to meet pstate latency hiding needs. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Dmytro Laktyushkin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-21drm/amd/display: Add FAMS capability to DCN31Aurabindo Pillai1-0/+1
DCN31 supports FAMS, but this was not correctly set to the hardware setup sequence. This commit fixes this issue by setting the MCLK switch capability based on the feature capability retrieved from the DMUB. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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