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path: root/drivers/gpu/drm/amd/display/dc/dce/Makefile
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2023-10-09drm/amd/display: Refactor HWSS into component folderMounika Adhuri1-1/+1
[why] Rename hw_sequencer to hwseq. Move all hwseq files to unique folder hwss. [how] creating hwss repo in dc, and moved the dcnxx_hwseq.c and .h files into corresponding new folders inside the hwss and cleared the linkage errors by adding relative paths in the Makefile.template. Reviewed-by: Martin Leung <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Mounika Adhuri <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-07drm/amd/display: Add Functions to enable Freesync Panel ReplayBhawanpreet Lakha1-1/+1
Add various functions for replay, such as construct, destroy, enable get_state, and copy_setting etc. These functions communicate with the firmware to setup and enable panel replay Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-18drm/amd/display: Refactor ABM featureLeon Huang1-1/+1
[Why] Refactor ABM feature and implement inbox command for DMUB. [How] Implement the ioctl to send inbox command to DMUB. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Leon Huang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-02drm/amd/display: Support for DMUB AUXMeenakshikumar Somasundaram1-1/+1
[WHY] To process AUX transactions with DMUB using inbox1 and outbox1 mail boxes. [HOW] 1) Added inbox1 command DMUB_CMD__DP_AUX_ACCESS to issue AUX commands to DMUB in dc_process_dmub_aux_transfer_async(). DMUB processes AUX cmd with DCN and sends reply back in an outbox1 message triggering an outbox1 interrupt to driver. 2) In existing driver implementation, AUX commands are processed synchronously by configuring DCN reg. But in DMUB AUX, driver sends an inbox1 message and waits for a conditional variable (CV) which will be signaled by outbox1 ISR. 3) As the driver holds dal and dc locks while waiting for CV, the outbox1 ISR is registered with noMutexWait set to true, which allows ISR to run and signal CV. This sets a constraint on ISR to not modify variables such as dc, dmub, etc. 4) Created dmub_outbox.c with dmub_enable_outbox_notification() to enable outbox1 mailbox. 5) New mailbox address ranges allocated for outbox1 of size DMUB_RB_SIZE. Created dmub functions for Outbox1: dmub_dcn20_setup_out_mailbox(), dmub_dcn20_get_outbox1_wptr() and dmub_dcn20_set_outbox1_rptr(). 6) Added functions dc_stat_get_dmub_notification() and dmub_srv_stat_get_notification() to retrieve Outbox1 message. 7) Currently, DMUB doesn't opens DDC in AUX mode before issuing AUX transaction. A workaround is added in dce_aux_transfer_dmub_raw() to open in DDC in AUX mode for every AUX transaction. 8) Added dc debug option enable_dmub_aux_for_legacy_ddc enable/disable DMUB AUX. This debug option is checked dce_aux_transfer_with_retries() to select the method to process AUX transactions. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Meenakshikumar Somasundaram <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-01drm/amd/display: Use dmub fw to lock pipe, cursor, digWyatt Wood1-1/+2
[Why] Hw lock manager adds the ability to lock pipe, cursor, and dig in fw. [How] Send hw lock command to fw to lock pipe, cursor, and dig. Signed-off-by: Wyatt Wood <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/display: change from panel to panel cntlAnthony Koo1-1/+1
[Why] it doesn't represent panel specifically, it's more like the control logic for the panel [How] change from panel to panel cntl to make it a bit more clear Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/display: move panel power seq to new panel structAnthony Koo1-1/+1
[Why] panel power sequencer is currently just sitting in hwseq but it really it tied to internal panels [How] make a new panel struct to contain power sequencer code Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-01drm/amd/display: Add ABM driver implementationWyatt Wood1-1/+1
[Why] Moving ABM from DMCU to DMCUB. [How] Add ABM driver files and implementation. Signed-off-by: Wyatt Wood <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-02-25drm/amd/display: Add driver support for enabling PSR on DMCUBWyatt Wood1-1/+1
[Why] We want to be able to enable PSR on DMCUB, and fallback to DMCU when necessary. [How] Add infrastructure to enable and disable PSR on DMCUB. Signed-off-by: Wyatt Wood <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-05-31drm/amd/display: move clk_mgr files to right placeEric Yang1-1/+1
[Why] Better organization [How] Move clk_mgr files under dc/clk_mgr Signed-off-by: Eric Yang <[email protected]> Reviewed-by: Yongqiang Sun <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-05-31drm/amd/display: make clk mgr soc specificEric Yang1-1/+1
[Why] First step of refactoring clk mgr to better handle different ways of handling clock operations. Clock operation policies are soc specific and not just DCN vesion specific. It is not a hw resource, should not be in the resource pool. [How] Change clock manager creation to be based on HW internal ID, rename clock manager members to be more clear. Move clock manager out of resource. Signed-off-by: Eric Yang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: rename dccg to clk_mgrDmytro Laktyushkin1-1/+1
In preparation for adding the actual dccg block since the current implementation of dccg is mor eof a clock manager than a hw block Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: split dccg clock manager into asic foldersDmytro Laktyushkin1-1/+1
Currently dccg contains code related to every dcn revision in a single file. This change splits out the dcn parts of code into correct folders Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-08-27drm/amd/display: Create new i2c resourceDavid Francis1-2/+2
[Why] I2C code did not match dc resource model and was generally unpleasant [How] Move code into new svelte dce_i2c files, replacing various i2c objects with two structs: dce_i2c_sw and dce_i2c_hw. Fully split sw and hw code paths. Remove all redundant declarations. Use address lists to distinguish between versions. Change dce80 code to newer register access macros. Signed-off-by: David Francis <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-24drm/amd/display: Decouple aux from i2cBhawanpreet Lakha1-1/+1
[Why] Aux engine is created from i2caux layer. We want to remove this layer and use the engine directly. [How] Decouple aux engine from i2caux. Move aux engine related code to dce folder and use dc resource pool to manage the engine. And use the engine functions directly Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu: add license to MakefilesAlex Deucher1-0/+21
Was missing license text. Acked-by: Harry Wentland <[email protected]> Acked-by: Felix Kuehling <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/display: dce120 to dce ipp refactorDmytro Laktyushkin1-1/+1
Signed-off-by: Dmytro Laktyushkin <[email protected]> Acked-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/display: DMCU Compile and LoadAnthony Koo1-1/+1
Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/display: OPP refactor and consolidation for DCE.Zeyu Fan1-1/+1
Signed-off-by: Zeyu Fan <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/display: consolidate dce8-11.2 display clock codeDmytro Laktyushkin1-1/+2
Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/dc: Add dc display driver (v2)Harry Wentland1-0/+14
Supported DCE versions: 8.0, 10.0, 11.0, 11.2 v2: rebase against 4.11 Signed-off-by: Harry Wentland <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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