| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2024-09-06 | drm/amd/display: fix dccg root clock optimization related hang | Qili Lu | 2 | -5/+10 | |
| [Why] enable dpp rcg before we disable dppclk in hw_init cause system hang/reboot [How] we remove dccg rcg related code from init into a separate function and call it after we init pipe Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Qili Lu <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-09-06 | drm/amd/display: Refactor dccg35_get_other_enabled_symclk_fe | Nicholas Susanto | 1 | -40/+25 | |
| [Why] Function used to check the number of FEs connected to the current BE. This was then used to determine if the symclk could be disabled, if all FEs were disconnected. However, the function would skip over the primary FE and return 0 when the primary FE was still connected. This caused black screens on driver disable with an MST daisy chain hooked up. [How] Refactor the function to correctly return the number of FEs connected to the input BE. Also, rename it for clarity. Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Nicholas Susanto <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-09-02 | drm/amd/display: Fix flickering caused by dccg | Hansen Dsouza | 2 | -28/+72 | |
| Always allow un-gating. Follow legacy workaround for repeated dppclk dto updates Reviewed-by: Muhammad Ahmed <[email protected]> Signed-off-by: Hansen Dsouza <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-08-27 | drm/amd/display: guard write a 0 post_divider value to HW | Ahmed, Muhammad | 1 | -1/+2 | |
| [why] post_divider_value should not be 0. Reviewed-by: Charlene Liu <[email protected]> Signed-off-by: Ahmed, Muhammad <[email protected]> Signed-off-by: Zaeem Mohamed <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-08-20 | Revert "drm/amd/display: Update to using new dccg callbacks" | Hansen Dsouza | 1 | -2/+2 | |
| [Why] Revert updated DCCG wrappers due to regression [How] This reverts commit 680458d41aa46a009909482f58358205b5c4b438. Reviewed-by: Chris Park <[email protected]> Signed-off-by: Hansen Dsouza <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-08-13 | drm/amd/display: Update to using new dccg callbacks | Hansen Dsouza | 1 | -2/+2 | |
| [Why and how] Update to using new dccg callbacks Reviewed-by: Chris Park <[email protected]> Signed-off-by: Hansen Dsouza <[email protected]> Signed-off-by: Tom Chung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-08-06 | drm/amd/display: Add clock control callbacks | Hansen Dsouza | 1 | -54/+99 | |
| [why & how] Add clock source selection control functions based on spec Reviewed-by: Muhammad Ahmed <[email protected]> Signed-off-by: Hansen Dsouza <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-08-06 | drm/amd/display: Add clock control callbacks | Hansen Dsouza | 1 | -29/+252 | |
| [why & how] Add clock source selection an control functions based on spec Reviewed-by: Muhammad Ahmed <[email protected]> Signed-off-by: Hansen Dsouza <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-08-06 | drm/amd/display: Add stream and char control callback | Hansen Dsouza | 1 | -10/+122 | |
| [why & how] Add new stream and char control functions based on DCCG spec Reviewed-by: Muhammad Ahmed <[email protected]> Signed-off-by: Hansen Dsouza <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-07-27 | drm/amd/display: Add new enable and disable functions for DCN35 | Hansen Dsouza | 1 | -1/+53 | |
| Add new enable and disable functions based on DCCG spec. Signed-off-by: Hansen Dsouza <[email protected]> Reviewed-by: Muhammad Ahmed <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-07-27 | drm/amd/display: Add new enable and disable functions | Hansen Dsouza | 1 | -0/+212 | |
| Add new enable and disable functions based on DCCG spec. Signed-off-by: Hansen Dsouza <[email protected]> Reviewed-by: Muhammad Ahmed <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-07-23 | drm/amd/display: Add source select helper functions | Hansen Dsouza | 1 | -0/+324 | |
| [why & how] Add source select helpers based on DCCG spec Reviewed-by: Daniel Miess <[email protected]> Signed-off-by: Hansen Dsouza <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-07-23 | drm/amd/display: Add RCG helper functions | Hansen Dsouza | 1 | -0/+307 | |
| [why & how] Add standard RCG helpers based on DCCG spec Reviewed-by: Daniel Miess <[email protected]> Reviewed-by: Muhammad Ahmed <[email protected]> Signed-off-by: Hansen Dsouza <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-07-23 | drm/amd/display: Add private data type for RCG | Hansen Dsouza | 1 | -0/+81 | |
| [why & how] Add private data types for better RCG control Reviewed-by: Chris Park <[email protected]> Reviewed-by: Yihan Zhu <[email protected]> Signed-off-by: Hansen Dsouza <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-07-23 | drm/amd/display: fix dscclk programming sequence on DCN401 | Wenjing Liu | 3 | -19/+23 | |
| [why] The mux to switch between refclk and dto_dsc_clk is non double buffered. However dto dsc clk's phase and modulo divider registers are currently configured as double buffered update. This causes a problem when we switch to use dto dsc clk and program phase and modulo in the same sequence. In this sequence dsc clk is switched to dto but the clock divider programming doesn't take effect until next frame. When we try to program DSCC registers, SMN bus will hang because dto dsc clk divider phase is set to 0. [how] Configure phase and modulo to take effect immediately. Always switch to dto dsc clk before DSC clock is unagted. Switch back to refclk after DSC clock is gated. Acked-by: Rodrigo Siqueira <[email protected]> Reviewed-by: Jerry Zuo <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-06-27 | drm/amd/display: Refactor dccg401_get_other_enable_symclk_fe | Relja Vojvodic | 1 | -35/+22 | |
| [WHY] Function was used to check the number of FEs connected to the current BE. This was then used to determine if the symclk could be disabled, if all FEs were disconnected. However, the function would skip over the primary FE and return 0 when the primary FE was still connected. This caused black screens on driver disable with an MST daisy chain hooked up. [HOW] Refactored the function to correctly return the number of FEs connected to the input BE. Also renamed it for clarity. Reviewed-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Relja Vojvodic <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-06-14 | drm/amd/display: Fix incorrect size calculation for loop in dcn401 | Alex Hung | 1 | -1/+1 | |
| [WHY] fe_clk_en and be_clk_sel have size of 4 but sizeof(fe_clk_en) has byte size 16 which is lager than the array size. [HOW] Use ARRAY_SIZE for calculating size. This fixes 2 OVERRUN issues reported by Coverity. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-06-14 | drm/amd/display: Avoid programming DTO if Refclk is 0 | Chris Park | 1 | -0/+4 | |
| [Why] Reference clock, either DPREFCLK or DTBCLK can be a value of 0 which then will encounter division by 0. [How] Avoid further calculation and programming if refclk is not populated. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Chris Park <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-06-05 | drm/amd/display: Keep VBios pixel rate div setting until next mode set | yi-lchen | 4 | -17/+25 | |
| [why] Vbios & Driver have difference pixel rate div policy. When enabling fast boot & performing blank & unblank w/o timing setting, pixel clock & pixel rate dividor are not match. It would cause too high pixel reate and eDP would be black screen. [How] We would keep pixel rate div setting by Vbios until next timing setting. Reviewed-by: Jun Lei <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: yi-lchen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-05-20 | drm/amd/display: Adjust incorrect indentations and spaces | Alex Hung | 1 | -1/+1 | |
| This fixes indentations and adjust spaces for better readability and code styles. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-05-20 | drm/amd/display: Add missing enable and disable symclk_se functions for dcn401 | Wenjing Liu | 2 | -0/+171 | |
| The functions are missing. These two functions are required to support MST. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-05-13 | Revert "drm/amd/display: Enable SYMCLK gating in DCCG" | Alex Hung | 1 | -57/+45 | |
| This reverts commit c49e44ede5cdfe650c2f769d8bd58cbe289e87cd. This causes regression on DP link layer test. Reported-by: Mark Broadworth <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-05-13 | drm/amd/display: Enable SYMCLK gating in DCCG | Daniel Miess | 1 | -45/+57 | |
| [WHY & HOW] Enable root clock optimization for SYMCLK and only disable it when it's actively used. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Daniel Miess <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-05-13 | drm/amd/display: Refactor DCN401 DCCG into component directory | Revalla Hari Krishna | 3 | -1/+1046 | |
| [WHY] Clean up the code that requires dccg to be in its own component. [HOW] Move all files under newly created dccg dir and fix the makefiles. Acked-by: Alex Hung <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Revalla Hari Krishna <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-05-02 | drm/amd/display: Fix incorrect size calculation for loop | Alex Hung | 1 | -1/+1 | |
| [WHY] fe_clk_en has size of 5 but sizeof(fe_clk_en) has byte size 20 which is lager than the array size. [HOW] Divide byte size 20 by its element size. This fixes 2 OVERRUN issues reported by Coverity. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-05-02 | drm/amd/display: Refactor DCCG into component folder | Revalla Hari Krishna | 21 | -0/+4835 | |
| [why] cleaning up the code refactor requires dccg to be in its own component. [how] move all files under newly created dccg folder and fixing the makefiles. Reviewed-by: Martin Leung <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Revalla Hari Krishna <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||