aboutsummaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd/display/dc/clk_mgr
AgeCommit message (Collapse)AuthorFilesLines
2024-09-18drm/amd/display: Block dynamic IPS2 on DCN35 for incompatible FW versionsNicholas Kazlauskas1-0/+6
[WHY] Hangs with Z8 can occur if running an older unfixed PMFW version. [HOW] Fallback to RCG only for dynamic IPS2 states if it's not newer than 93.12. Limit to DCN35. Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Reviewed-by: Charlene Liu <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-09-18drm/amd/display: Emulate Display Hotplug HangDaniel Sa1-7/+2
[WHY] Driver reports 0 display when the virtual display is still present, and causes P-state hang in FW. [HOW] When enumerating through streams, check for active planes and use that to indicate number of displays. Reviewed-by: Dillon Varone <[email protected]> Signed-off-by: Daniel Sa <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-09-02drm/amd/display: Fix DCN35 set min dispclk logicNicholas Susanto1-3/+3
[Why] Setting min dispclk to 50Mhz outside clock lowering function causes unnecessary calls to SMU to lower dispclk and causes dentist hangs when there is no stream on the pipes. [How] Move the set minimum dispclk logic inside the lowering dispclk if statement. Fixes: 234441320552 ("DCN35 set min dispclk to 50Mhz") Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Nicholas Susanto <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-08-27drm/amd/display: Allocate DCN35 clock table transfer buffers in GARTNicholas Kazlauskas1-3/+3
[Why] Request from PMFW to use GART for clock table transfer tables as framebuffer is being deprecated on APU. [How] Switch over to GART via the allocation flag. Reviewed-by: Sung joon Kim <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Zaeem Mohamed <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-08-27drm/amd/display: Don't skip clock updates in overclockingAlvin Lee1-3/+0
[Description] Skipping clock updates is not a hard requirement for overclocking and only an optimization. Remove the skip as this can cause issues for FAMS transitions during the overclock sequence. If FAMS is enabled we must disable UCLK switch on any full update (which requires update clocks to be called). Reviewed-by: Dillon Varone <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Zaeem Mohamed <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-08-20drm/amd/display: DCN35 set min dispclk to 50MhzNicholas Susanto1-0/+3
[Why] Causes hard hangs when resuming after display off on extended/duplicate modes [How] Set the min dispclk to 50Mhz for DCN35 Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Nicholas Susanto <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-08-13drm/amd/display: guard otg disable w/a for testMuhammad Ahmed1-0/+3
[why & how] HW removed this w/a, but we will still keep it to avoid regression. but return in test mode. Reviewed-by: Charlene Liu <[email protected]> Signed-off-by: Muhammad Ahmed <[email protected]> Signed-off-by: Tom Chung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-08-06drm/amd/display: Address coverity changeChris Park1-2/+4
[Why] Coverity picks up a defect with regards to array underflow. [How] Address coverity issue as recommended. Reviewed-by: Leo Ma <[email protected]> Signed-off-by: Chris Park <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-27drm/amd/display: restore immediate_disable_crtc for w/aCharlene Liu1-2/+2
[why] immediate_disable_crtc does not reset ODM. if switching to disable_crtc which will disable ODM as well. i.e. need to restore ODM mem cfg at reenable it at end of w/a. Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Xi (Alex) Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Fix Potential Null DereferenceGabe Teeger1-3/+3
[what & why] System hang after s4 regression points to code change here. Removing possible NULL dereference. Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Gabe Teeger <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Remove hardmax usage for dcn401Dillon Varone1-21/+23
[WHY&HOW] Hardmax message will be retired for dcn4, so this removes it. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Check null pointers before usedAlex Hung1-1/+1
[WHAT & HOW] Poniters, such as dc->clk_mgr, are null checked previously in the same function, so Coverity warns "implies that "dc->clk_mgr" might be null". As a result, these pointers need to be checked when used again. This fixes 10 FORWARD_NULL issues reported by Coverity. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: avoid disable otg when dig was disabledJingwen Zhu1-3/+15
[Why] This is a workaround for an dcn3.1 hang that happens if otg dispclk is ramped while otg is on and stream enc is off. But this w/a should not trigger when we have a dig active. [How] Avoid disable otg when dig FE/BE FIFO was not switched. Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Jingwen Zhu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Added logging for automated DPM testingRyan Seto1-53/+197
[Why] Added clock logs to automate DPM testing [How] Added logs and helper functions to output clocks Co-authored-by: Ryan Seto <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Ryan Seto <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-01drm/amd/display: replace CRTC disable function callXi (Alex) Liu1-2/+2
[Why] In OTG disable workarund, CRTC is disabled immediately to improve performance, but this may cause timing issue in DP HPO encoder FIFO and result in blank CRCs. [How] Replace the immediate CRTC disable call with normal disable call Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Xi (Alex) Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-01drm/amd/display: fix a crash when clock source is reference for non otg ↵Wenjing Liu1-18/+20
master pipe [why] The function enumerates all pipes without checking pipe type. It is only supposed to call program pixel clock for OTG master pipe only. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-01drm/amd/display: Cleanup dce_get_dp_ref_freq_khzDillon Varone1-1/+1
[WHY&HOW] Cleanup unnecessary code pathes as compile guards were added and removed overtime. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-01drm/amd/display: Fix possible overflow in integer multiplicationAlex Hung1-1/+1
[WHAT & HOW] Integer multiplies integer may overflow in context that expects an expression of unsigned/siged long long (64 bits). This can be fixed by casting integer to unsigned/siged long long to force 64 bits results. This fixes 26 OVERFLOW_BEFORE_WIDEN issues reported by Coverity. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-27drm/amd/display: Add null checks before accessing struct elementsAlex Hung2-8/+12
[WHAT] 1. is_pwrseq0 needs to check link before accessing link->link_index. 2. context is checked before accessing its bw_ctx.dml2 3. clk_mgr_base->bw_params is checked before clk_table.num_entries_per_cl This fixes 4 REVERSE_INULL issues reported by Coverity. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-27drm/amd/display: Remove useless function callAlex Hung1-2/+0
[WHAT & HOW] clk_mgr_helper_get_active_display_cnt returns display count and itself alone has no use. This fixes 1 CHECKED_RETURN issue reported by Coverity. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-19drm/amd/display: Remove redundant null checksAlex Hung1-1/+1
The null checks are redundant as they were already dereferenced previously, as reported by Coverity; therefore the null checks are removed. This fixes 7 REVERSE_INULL issues reported by Coverity. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-19drm/amd/display: Remove redundant checks for ctx->dc_biosAlex Hung7-7/+7
The null checks for ctx->dc_bios are redundant as it was already dereferenced previously, as reported by Coverity; therefore the null checks are removed. This fixes 7 REVERSE_INULL issues reported by Coverity. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Send message to notify the DPIA host router bandwidthSung Joon Kim3-1/+77
[why] Tell the system about the current host router bandwidth to be used to measure and calculate the right voltage to be used. [how] Send SMU message of each DPIA host router bandwidth. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: On clock init, maintain DISPCLK freqChris Park1-0/+17
[Why] On init if a display is connected, we need to maintain the DISPCLK frequency Even though DPG_EN=1, the display still requires the correct timing or it could cause audio corruption (if DISPCLK freq is reduced). [How] Read the current DISPCLK freq and request the same value to ensure the timing is valid and unchanged. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Chris Park <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Update idle hardmins if uclk or fclk requirement changedDillon Varone1-1/+1
[WHY&HOW] Update the idle hardmin with SMU if either clock changed. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Remove useless comparison of unsigned int vs. 0Alex Hung2-8/+8
[WHY & HOW] The comparisons of unsigned int with 0 can have no meanings, i.e. unsigned int >= 0 (always true) or unsigned int < 0 (always false), and therefore they are removed. This fixes 12 NO_EFFECT issues reported by Coverity. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Remove duplicate 'update_idle_uclk' in dcn401 clk_mgr codeIvan Lipski1-1/+1
[WHY] The coverity analysis flagged this if expression as it contains a 'CONSTANT_EXPRESSION_RESULT': 'update_idle_uclk' is 'ORd' with itself. [HOW] Removed the duplicate 'update_idle_uclk'. Reviewed-by: Alex Hung <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Remove dcn32_smu13 duplicate headerZaeem Mohamed3-110/+2
[WHY] Duplicate headers requiring unecessary maintenance of both headers [HOW] Removal of smu13_driver_if header and all referneces to it changed to dcn32_smu13_driver Signed-off-by: Zaeem Mohamed <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Force max clocks unconditionally when p-state is unsupportedDillon Varone1-16/+20
[WHY&HOW] UCLK and FCLK are updated together, so an FCLK update can also cause UCLK update to SMU. When this happens, the UCLK provided should be max if switching is unsupported. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-05drm/amd/display: Add UCLK p-state support message to dcn401Dillon Varone4-54/+102
[WHY&HOW] Improves on the SMU interface to explicitly declare P-State support. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-05drm/amd/display: Wait for hardmins to complete on dcn401Dillon Varone2-4/+112
[WHY&HOW] When updating clocks via SMU, DAL needs to wait for requests to be fulfilled before proceeding. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-20drm/amd/display: Correct display clocks update block sequenceDillon Varone2-313/+272
[WHY&HOW] At the time of block sequence construction, the exact reference DPP/DISP clock is not yet known, so the clock should be passed by reference to the DTO programming function. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-20drm/amd/display: Adjust incorrect indentations and spacesAlex Hung2-2/+0
This fixes indentations and adjust spaces for better readability and code styles. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-13drm/amd/display: Refactor dcn401_update_clocksDillon Varone5-5/+710
[WHY & HOW] Refactor complex code into manageable functions. This also cleans up some updating logics. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-13drm/amd/display: Disable AC/DC codepath when unnecessaryJoshua Aberback1-7/+21
[WHY] If there are no DC clock limits present, or if the DC limits are the same as the AC limits, we can disable the AC/DC codepath as there won't be any validation differences between the two modes. [HOW] When all DC power mode clock limits are the same as the max clock values, there won't be any difference between AC mode and DC mode. Zero out DC limits that equal max and provide a new cap to indicate the presence of any non-zero DC mode limit. In summary: - zero out DC limits that are the same as max clock value - new dc cap to indicate the presence of DC mode limits - set limits present if any clock has distinct AC and DC values from SMU Acked-by: Alex Hung <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Joshua Aberback <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-13drm/amd/display: Create dcn401_clk_mgr structDillon Varone3-10/+26
Create dcn401 specific structure to encapsulate version specific variables. Acked-by: Alex Hung <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amd/display: Limit clock assignments by size of clk tablesAlex Hung1-1/+1
[WHAT & HOW] Check clk table's array size to avoid out-of-bound memory accesses. This fixes two OVERRUN issues reported by Coverity. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amd/display: Check num_valid_sets before accessing reader_wm_sets[]Alex Hung1-1/+2
[WHY & HOW] num_valid_sets needs to be checked to avoid a negative index when accessing reader_wm_sets[num_valid_sets - 1]. This fixes an OVERRUN issue reported by Coverity. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amd/display: Fix invalid Copyright noticeLeo Ma2-2/+2
[Why && How] Copyright notice failed in the Palamida scan and make changes to align with our guidelines. Acked-by: Tom Chung <[email protected]> Signed-off-by: Leo Ma <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Remove duplicate dcn401/dcn401_clk_mgr.h headerJiapeng Chong1-1/+0
./drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c: dcn401/dcn401_clk_mgr.h is included more than once. Reported-by: Abaci Robot <[email protected]> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=8885 Signed-off-by: Jiapeng Chong <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Fix DC mode screen flickering on DCN321Leo Ma1-3/+12
[Why && How] Screen flickering saw on 4K@60 eDP with high refresh rate external monitor when booting up in DC mode. DC Mode Capping is disabled which caused wrong UCLK being used. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Leo Ma <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Add dtbclk access to dcn315Swapnil Patel1-0/+8
[Why & How] Currently DCN315 clk manager is missing code to enable/disable dtbclk. Because of this, "optimized_required" flag is constantly set and this prevents FreeSync from engaging for certain high bandwidth display Modes which require DTBCLK. Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Swapnil Patel <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-26drm/amd/display: Add misc DC changes for DCN401Aurabindo Pillai2-0/+25
Add miscellaneous changes to enable DCN401 init Signed-off-by: Aurabindo Pillai <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-26drm/amd/display: Add new DCN401 sourcesAurabindo Pillai6-0/+1281
Add initial support for DCN 4.0.1. Signed-off-by: Aurabindo Pillai <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-26drm/amd/display: Add NULL pointer check for kzallocHersen Wu2-0/+16
[Why & How] Check return pointer of kzalloc before using it. Reviewed-by: Alex Hung <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Hersen Wu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-23drm/amd/display: Remove duplicate dcn32/dcn32_clk_mgr.h headerJiapeng Chong1-1/+0
./drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c: dcn32/dcn32_clk_mgr.h is included more than once. Reported-by: Abaci Robot <[email protected]> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=8789 Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Jiapeng Chong <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-16drm/amd/display: Improve the log precisionEthan Bitnun1-1/+1
The previous assumption that there will be an optimize_bandwidth call following every prepare_bandwidth call was incorrect and caused small inaccuracies in logging, as some info was only updated in later prepare calls. Reviewed-by: Leo Li <[email protected]> Signed-off-by: Ethan Bitnun <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-16drm/amd/display: Adjust headersRodrigo Siqueira1-0/+1
Update headers by removing two unecessary headers and include a new one. Reviewed-by: Leo Li <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-16drm/amd/display: Use dce_version instead of chip_idRodrigo Siqueira1-1/+1
The chip ID DEVICE_ID_NV_13FE is not meaningful and represents a legacy way of dealing with chip ID. This commit uses dc_version instead of chip_id and also DCN_VERSION_2_01 instead of DEVICE_ID_NV_13FE. Signed-off-by: Rodrigo Siqueira <[email protected]> Reviewed-by: Leo Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-12drm/amd/display: Adjust some includes used by displayRodrigo Siqueira5-5/+1
Some of the includes used in the DC can be removed and others need to be update. This commit adjusts some of those headers in the display code. Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.