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path: root/drivers/gpu/drm/amd/display/dc/Makefile
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2024-07-27drm/amd/display: Refactor for dioBhuvanachandra Pinninti1-1/+0
Moved files to respective folders to improve DIO code. Signed-off-by: Bhuvanachandra Pinninti <[email protected]> Reviewed-by: Martin Leung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Refactor DCN3X into component folderMounika Adhuri1-5/+1
[why] Move DCN3X files to unique component folder. [how] Create respective component folder in dc, move the DCN3X files into corresponding new folders and made appropriate changes for compilation in Makefiles. Reviewed-by: Martin Leung <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Mounika Adhuri <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-08drm/amd/display: Refactor HUBP into component folder.Bhuvana Chandra Pinninti1-1/+1
[why] cleaning up the code refactor requires hubp to be in its own component. [how] move all files under newly created hubp folder and fixing the makefiles. Reviewed-by: Martin Leung <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Bhuvana Chandra Pinninti <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amd/display: Refactor DCCG into component folderRevalla Hari Krishna1-1/+1
[why] cleaning up the code refactor requires dccg to be in its own component. [how] move all files under newly created dccg folder and fixing the makefiles. Reviewed-by: Martin Leung <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Revalla Hari Krishna <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Refactor HUBBUB into component folderRevalla Hari Krishna1-1/+1
[why] cleaning up the code refactor requires hubbub to be in its own component. [how] Move all files under newly created hubbub folder and fix the makefiles. Reviewed-by: Martin Leung <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Revalla Hari Krishna <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-26drm/amd/display: Add misc DC changes for DCN401Aurabindo Pillai1-0/+9
Add miscellaneous changes to enable DCN401 init Signed-off-by: Aurabindo Pillai <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-03-20drm/amd/display: Refactor DPP into a component directoryRevalla Hari Krishna1-1/+1
[WHY & HOW] Move all dpp files to a new dpp directory. Reviewed-by: Martin Leung <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Revalla Hari Krishna <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-03drm/amd/display: Refactor INIT into component folderRevalla1-2/+0
[why] Move all init files to hwss folder. [how] moved the dcnxx_init.c and .h files into inside the hwss and cleared the linkage errors. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Martin Leung <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Revalla <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-19drm/amd/display: Refactor dc_state interfaceDillon Varone1-1/+1
[WHY?] Part of the dc_state interface that deals with adding streams and planes should remain public, while others that deal with internal status' and subvp should be private to DC. [HOW?] Move and rename the public functions to dc_state.h and private functions to dc_state_priv.h. Also add some additional functions for extracting subvp meta data from the state. Reviewed-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amd/display: Refactor OPTC into component folderParandhaman K1-1/+1
[why] Move all optc files to unique folder optc. [how] creating optc repo in dc, and moved the dcnxx_optc.c and .h files into corresponding new folders inside the optc and cleared the linkage errors by adding relative paths in the Makefile.template. Reviewed-by: Martin Leung <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Parandhaman K <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-17drm/amd/display: Refactor resource into component directoryMounika Adhuri1-4/+1
[WHY] Move all resource files to unique folder resource. [HOW] Created resource folder in dc, moved the dcnxx_resource.c and dcnxx_resource.h files into corresponding new folders inside the resource and made appropriate changes for compilation in Makefiles. Reviewed-by: Martin Leung <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Mounika Adhuri <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Refactor HWSS into component folderMounika Adhuri1-1/+1
[why] Rename hw_sequencer to hwseq. Move all hwseq files to unique folder hwss. [how] creating hwss repo in dc, and moved the dcnxx_hwseq.c and .h files into corresponding new folders inside the hwss and cleared the linkage errors by adding relative paths in the Makefile.template. Reviewed-by: Martin Leung <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Mounika Adhuri <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Introduce DML2Qingqing Zhuo1-1/+2
DC is transitioning from DML to DML2, and this commit introduces all the required changes for some of the already available ASICs and adds the required code infra to support new ASICs under DML2. DML2 is also a generated code that provides better mode verification and programming models for software/hardware, and it enables a better way to create validation tools. This version is more like a middle step to the complete transition to the DML2 version. Changes since V1: - Alex: Fix typos Changes since V2: - Update DC includes Changes since V3: - Fix 32 bit compilation issues on x86 Changes since V4: - Avoid compilation of DML2 on some not supported 32-bit architecture - Update commit message Co-developed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Co-developed-by: Roman Li <[email protected]> Signed-off-by: Roman Li <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Move dml code under CONFIG_DRM_AMD_DC_FP guardRodrigo Siqueira1-1/+2
For some reason, the dml code is not guarded under CONFIG_DRM_AMD_DC_FP in the Makefile. This commit moves the dml code under the DC_FP guard. Reviewed-by: Qingqing Zhuo <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add DCN35 blocks to MakefileQingqing Zhuo1-0/+1
[Why & How] Enable DCN35 in makefile. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Remove wait while lockedGabe Teeger1-0/+1
[Why] We wait for mpc idle while in a locked state, leading to potential deadlock. [What] Move the wait_for_idle call to outside of HW lock. This and a call to wait_drr_doublebuffer_pending_clear are moved added to a new static helper function called wait_for_outstanding_hw_updates, to make the interface clearer. Cc: [email protected] Fixes: 8f0d304d21b3 ("drm/amd/display: Do not commit pipe when updating DRR") Reviewed-by: Jun Lei <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Gabe Teeger <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: Rename DCN config to FPHarry Wentland1-1/+1
[Why & How] The only reason we have the DCN config is for floating point support. Rename it to make that clear and (hopefully) avoid misuse of the config in the future. Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: Build DSC without DCN configHarry Wentland1-2/+1
[Why & How] DSC needs DCN but we are trying reduce the usage of the DCN flag. It's easier to build the DSC code sprinkled around DC core and the DMs and just guard the place where DSC uses floating point code. Since DSC is never enabled on non-DCN ASICs this won't have any effect. Reviewed-by: Hamza Mahfooz <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: Drop CONFIG_DRM_AMD_DC_HDCPHarry Wentland1-2/+0
[Why & How] There is no reason we still need a config option for this. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-02-14drm/amd/display: move public dc link function implementation to dc_link_exportsWenjing Liu1-1/+1
[why] Link is a subcomponent in dc. DM should be aware of dc link structure as one of the abstracted objects maintained by dc. However it should have no idea of the existence of a link component in dc dedicated to maintain the states of dc link structure. As such we are moving link interfaces out of dc_link.h and directly added to dc.h. We are grandually fading out the explicit inclusion of dc_link header and eventually delete it. On dc side, since link is a subcomponent behind dc interfaces, it is not a good idea to implement dc interfaces in each individual subcomponent of link which is already a subcomponent of dc. So we are decoupling it by implementing a dc_link_exports in dc. This file will be a thin translation layer that breaks the dependency so link is able to make interface changes without breaking DM. Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-02-08drm/amd/display: break down dc_link.cWenjing Liu1-1/+1
[why] dc_link contains over 30k line of code, the decision is to break it down to files residing in link folder based on functionality. This change is the last break down change which will remove dc_link.c file after everything is broken down. [how] Move remaining dc_link.c functions into link_detection, link_dpms, link_validation, link_resource, and link_fpga and remove dc_link. Reviewed-by: George Shen <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-24drm/amd/display: merge dc_link_dp into dc_linkWenjing Liu1-2/+1
[why] Temporarly merge dc_link_dp functions into dc_link for the purpose of removing dc_link_dp files. This is a transitional change for later commits where we will further refactor dc_link file. Reviewed-by: George Shen <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-13drm/amd/display: move dc_link_dpia logic to link_dp_dpiaWenjing Liu1-1/+1
Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: George Shen <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-13drm/amd/display: move dpcd logic from dc_link_dpcd to link_dpcdWenjing Liu1-1/+1
[why] Moving dpcd logic from dc_link_dpcd to link_dpcd as part of link file restructure Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: George Shen <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-13drm/amd/display: refactor ddc logic from dc_link_ddc to link_ddcWenjing Liu1-2/+2
[why] 1. Move dd_link_ddc functions to link_ddc. 2. Move link ddc functions declaration exposed in dc to link.h 3. Move link ddc functions declaration exposed in dm to dc_link.h 4. Remove i2caux_interface.h file Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-18drm/amd/display: Enable building new display engine with KCOV enabledGuenter Roeck1-0/+3
The new display engine uses floating point math, which is not supported by KCOV. Commit 9d1d02ff3678 ("drm/amd/display: Don't build DCN1 when kcov is enabled") tried to work around the problem by disabling CONFIG_DRM_AMD_DC_DCN if KCOV_INSTRUMENT_ALL and KCOV_ENABLE_COMPARISONS are enabled. The result is that KCOV can not be enabled on systems which require this display engine. A much simpler and less invasive solution is to disable KCOV selectively when compiling the display enagine while keeping it enabled for the rest of the kernel. Fixes: 9d1d02ff3678 ("drm/amd/display: Don't build DCN1 when kcov is enabled") Cc: Arnd Bergmann <[email protected]> Cc: Leo Li <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Guenter Roeck <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-13drm/amd/display: Enable DCN314 in DCRoman Li1-0/+1
Add support for DCN 3.1.4 in Display Core Signed-off-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-08drm/amd/display: fix 32 bit compilation errors in dc_dmub_srv.cAlex Deucher1-26/+0
There are several things wrong here. First, none of these numbers are FP, so there is no need to cast to double. Next make sure to use proper 64 bit division helpers. Fixes: 85f4bc0c333c ("drm/amd/display: Add SubVP required code") Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-05drm/amd/display: Add SubVP required codeAlvin Lee1-1/+26
This commit enables the SubVP feature. To achieve that, we need to: - Don't force p-state disallow on SubVP (can't block dummy p-state) - Send calculated watermark to DMCUB for SubVP - Adjust CAB mode message to PMFW - Add a proper locking sequence for SubVP - Various fixes to SubVP static analysis and determining SubVP config - Currently SubVP not supported with pipe split so merge all pipes before setting up SubVp Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-03drm/amd/display: Add dependant changes for DCN32/321Aurabindo Pillai1-0/+2
[Why&How] This patch adds necessary changes needed in DC files outside DCN32/321 specific tree v2: squash in updates (Alex) Signed-off-by: Aurabindo Pillai <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-10drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dcAlex Hung1-2/+0
[Why & How] CONFIG_DRM_AMD_DC_DCN is used by pass the compilation failures, but DC code should be OS-agnostic. This patch fixes it by removing unnecessasry CONFIG_DRM_AMD_DC_DCN in dc and dc/core directories. Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-18drm/amd/display: Add DCN315 blocks to MakefileQingqing Zhuo1-0/+1
Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-17drm/amd/display: Add DCN316 resource and SMU clock managerHansen Dsouza1-0/+1
Add core DC implementation for DCN316. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Prike Liang <[email protected]> Reviewed-by: Leo Li <[email protected]> Signed-off-by: Hansen Dsouza <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-02drm/amd/display: move link_hwss to link folder and break down to filesWenjing Liu1-2/+2
[why] Move link_hwss to its own folder as part of DC LIB and break it down to separate file one for each type of backend for code isolation. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-01-18drm/amd/display: move calcs folder into DMLIsabella Basso1-2/+2
The calcs folder has FPU code on it, which should be isolated inside the DML folder as per https://patchwork.freedesktop.org/series/93042/. This commit aims single-handedly to correct the location of such FPU code and does not refactor any functions. Changes since v2: - Corrected problems to compile when DCN was disabled. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Isabella Basso <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-06drm/amd/display: Add stub to get DPIA tunneling device dataJimmy Kizito1-1/+1
[why & how] 1. Add stub for getting tunneling device data 2. Add check for phy_repeater_cnt < 0xff to LTTPR check 3. Add two more bits of information to DPIA links Reviewed-by: Jun Lei <[email protected]> Acked-by: Wayne Lin <[email protected]> Acked-by: Nicholas Kazlauskas <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Jimmy Kizito <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amdgpu/display: fold DRM_AMD_DC_DCN201 into DRM_AMD_DC_DCNAlex Deucher1-2/+0
No need for a separate kconfig option at this point. Reviewed-by: Zhan Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amd/display: add cyan_skillfish display supportZhan Liu1-0/+3
[Why] add display related cyan_skillfish files in. makefile controlled by CONFIG_DRM_AMD_DC_DCN201 flag. v2: squash in clang fixes from Harry, Nathan v3: squash in missing CONFIG_DRM_AMD_DC check (Alex) Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Zhan Liu <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Jun Lei <[email protected]> Acked-by: Harry Wentland <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-22drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCNAlex Deucher1-2/+0
No need for a separate flag now that DCN3.1 is not in bring up. Fold into DRM_AMD_DC_DCN like previous DCN IPs. Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Enforce DPCD Address rangesWesley Chalmers1-1/+1
[WHY] Some DPCD addresses, notably LTTPR Capability registers, are expected to be read all together in a single DPCD transaction. Rather than force callers to read registers they don't need, we want to quietly extend the addresses read, and only return back the values the caller asked for. This does not affect DPCD writes. [HOW] Create an additional layer above AUX to perform 'checked' DPCD transactions. Iterate through an array of DPCD address ranges that are marked as being contiguous. If a requested read falls within one of those ranges, extend the read to include the entire range. After DPCD has been queried, copy the requested bytes into the caller's data buffer, and deallocate all resources used. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: Add DCN3.1 blocks to the DC MakefileNicholas Kazlauskas1-0/+3
Preparation for compiling DCN3.1 support. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Initial DC support for Beige GobyAurabindo Pillai1-0/+1
[Why&How] Add Beige Goby (DCN303) resource, irq service, & dmub loader. v2: fix nbio include (Alex) Signed-off-by: Chris Park <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-10drm/amd/display: Support for DMUB AUXJude Shih1-1/+1
[WHY] To process AUX transactions with DMUB using inbox1 and outbox1 mail boxes. [How] 1) Added inbox1 command DMUB_CMD__DP_AUX_ACCESS to issue AUX commands to DMUB in dc_process_dmub_aux_transfer_async(). DMUB processes AUX cmd with DCN and sends reply back in an outbox1 message triggering an outbox1 interrupt to driver. 2) In existing driver implementation, AUX commands are processed synchronously by configuring DCN reg. But in DMUB AUX, driver sends an inbox1 message and waits for a conditional variable (CV) which will be signaled by outbox1 ISR. 3) DM will retrieve Outbox1 message and send back reply to upper layer and complete the AUX command Signed-off-by: Jude Shih <[email protected]> Reviewed-by: Hanghong Ma <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: Add dynamic link encoder selection.Jimmy Kizito1-2/+3
[Why] Some display endpoints may be programmably mapped to compatible link encoders. The assignment of link encoders to links has to be dynamic to accommodate the increased flexibility in comparison to conventional display endpoints. [How] - Add link encoder assignment tracking variables. - Execute link encoder assignment algorithm before enabling link and release link encoders from links once they are disabled. Signed-off-by: Jimmy Kizito <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-02drm/amd/display: Support for DMUB AUXMeenakshikumar Somasundaram1-1/+1
[WHY] To process AUX transactions with DMUB using inbox1 and outbox1 mail boxes. [HOW] 1) Added inbox1 command DMUB_CMD__DP_AUX_ACCESS to issue AUX commands to DMUB in dc_process_dmub_aux_transfer_async(). DMUB processes AUX cmd with DCN and sends reply back in an outbox1 message triggering an outbox1 interrupt to driver. 2) In existing driver implementation, AUX commands are processed synchronously by configuring DCN reg. But in DMUB AUX, driver sends an inbox1 message and waits for a conditional variable (CV) which will be signaled by outbox1 ISR. 3) As the driver holds dal and dc locks while waiting for CV, the outbox1 ISR is registered with noMutexWait set to true, which allows ISR to run and signal CV. This sets a constraint on ISR to not modify variables such as dc, dmub, etc. 4) Created dmub_outbox.c with dmub_enable_outbox_notification() to enable outbox1 mailbox. 5) New mailbox address ranges allocated for outbox1 of size DMUB_RB_SIZE. Created dmub functions for Outbox1: dmub_dcn20_setup_out_mailbox(), dmub_dcn20_get_outbox1_wptr() and dmub_dcn20_set_outbox1_rptr(). 6) Added functions dc_stat_get_dmub_notification() and dmub_srv_stat_get_notification() to retrieve Outbox1 message. 7) Currently, DMUB doesn't opens DDC in AUX mode before issuing AUX transaction. A workaround is added in dce_aux_transfer_dmub_raw() to open in DDC in AUX mode for every AUX transaction. 8) Added dc debug option enable_dmub_aux_for_legacy_ddc enable/disable DMUB AUX. This debug option is checked dce_aux_transfer_with_retries() to select the method to process AUX transactions. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Meenakshikumar Somasundaram <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-02drm/amd/display: Add Freesync HDMI support to DMCUStylon Wang1-1/+3
[Why] Adding support for Freesync HDMI to DC and DMCU [How] Create DC interface and implementation on top of DMCU to support parsing CEA blocks in DMCU. Signed-off-by: Stylon Wang <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-11-04drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)Alex Deucher1-10/+0
Avoids confusion in configurations. v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled v3: rebase on latest code Reviewed-by: Luben Tuikov <[email protected]> (v1) Signed-off-by: Alex Deucher <[email protected]>
2020-10-12drm/amd/display: Add support for DCN302 (v2)Bhawanpreet Lakha1-0/+5
- add DCN302 resource, irq service, dmub loader, - handle DC_VERSION_DCN_3_02 - define DCN302 power gating functions - handle DCN302 in GPIO files - define I2C regs - add CONFIG_DRM_AMD_DC_DCN3_02 guard v2: rebase fixes (Alex) Signed-off-by: Joshua Aberback <[email protected]> Signed-off-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: Add dcn3.01 support to DC (v2)Roman Li1-0/+4
Update dc for vangogh support. v2: fix compilation without DCN 301 set. Signed-off-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-27drm/amd/display: dc/dce: add initial DCE6 support (v10)Mauro Rossi1-0/+4
[Why] DCE6 chipsets have a lot in common with DCE8, let's start from this [How] DCE6 targets are added replicating existing DCE8 implementation. NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h initial build prototype due to missing DCE6 macros/registers/masks DCE6 specific macros/registers/masks will be added with later commits (v2b) removed dce_version cases in dc/dce/dce_clock_source.c and updated dce60 due to following kernel 5.0 commits: 24f7dd7 ("drm/amd/display: move pplib/smu notification to dccg block") 9566b67 ("drm/amd/display: remove safe_to_lower flag from dc, use 2 functions instead") 4244381 ("drm/amd/display: clean up base dccg struct") 4c5e8b5 ("drm/amd/display: split dccg clock manager into asic folders") 84e7fc0 ("drm/amd/display: rename dccg to clk_mgr") 77f6916 ("drm/amd/display: Remove duplicate header") 9f7ddbe ("drm/amd/display: fix optimize_bandwidth func pointer for dce80") 4ece61a ("drm/amd/display: set clocks to 0 on suspend on dce80") (v3b) updated dce60 due to following kernel 5.1 commits: 380604e ("drm/amd/display: Use 100 Hz precision for pipe pixel clocks") 32e6136 ("drm/amd/display: Fix 64-bit division for 32-bit builds") 1877ccf ("drm/amd/display: Change from aux_engine to dce_aux") c69dffa ("drm/amd/display: fix eDP fast bootup for pre-raven asic") (v4b) updated dce60 due to following kernel 5.2 commits: e5c4197 ("drm/amd/display: Add plane capabilities to dc_caps") 813d20d ("drm/amd/display: Fix multi-thread writing to 1 state") ea36ad3 ("drm/amd/display: expand plane caps to include fp16 and scaling capability") afcd526 ("drm/amd/display: Add fast_validate parameter") (v5b) updated dce60 due to following kernel 5.3 commits: e7e10c4 ("drm/amd/display: stop external access to internal optc sync params") 78cc70b ("drm/amd/display: Engine-specific encoder allocation") dc88b4a ("drm/amd/display: make clk mgr soc specific") 4fc4dca ("drm/amd: drop use of drmp.h in os_types.h") (v6b) updated dce60 due to following kernel 5.4 commits: 54a9bcb ("drm/amd/display: Fix a typo - dce_aduio_mask --> dce_audio_mask") 9adc805 ("drm/amd/display: make firmware info only load once during dc_bios create") (v7b) updated dce60 due to following kernel 5.5 commits: cabe144 ("drm/amd/display: memory leak") 8276dd8 ("drm/amd/display: update register field access mechanism") f6040a4 ("drm/amd/display: configurable aux timeout support") bf7f5ac ("drm/amd/display: map TRANSMITTER_UNIPHY_x to LINK_REGS_x") (v8b) updated dce60 due to following kernel 5.6 commits: d9e3267 ("drm/amd/display: cleanup of construct and destruct funcs") f42ea55 ("drm/amd/display: add separate of private hwss functions") (v9b) updated dce60 due to following kernel 5.8 commits: bba8289 ("drm/amd/display: code clean up in dce80_hw_sequencer.c") 904fb6e ("drm/amd/display: move panel power seq to new panel struct") d4caa72 ("drm/amd/display: change from panel to panel cntl") (v10) Fix up PLL handling for DCE6: DCE6.0 supports 2 PLLs. DCE6.1 supports 3 PLLs. (Alex) Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Mauro Rossi <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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