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2024-03-31fpga: xilinx-selectmap: add new driverCharles Perry1-0/+8
Xilinx 7 series FPGA can be programmed using a parallel port named the SelectMAP interface in the datasheet. This interface is compatible with the i.MX6 EIM bus controller but other types of external memory mapped parallel bus might work. xilinx-selectmap currently only supports the x8 mode where data is loaded at one byte per rising edge of the clock, with the MSb of each byte presented to the D0 pin. Signed-off-by: Charles Perry <[email protected]> [[email protected]: replace data type of i from u32 to size_t] Acked-by: Xu Yilun <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xu Yilun <[email protected]>
2024-03-31fpga: xilinx-spi: extract a common driver coreCharles Perry1-0/+4
Factor out the gpio handshaking (using PROGRAM_B, INIT_B and DONE) protocol in xilinx-core so that it can be reused for another driver. This commit does not change anything functionally to xilinx-spi. xilinx-core expects drivers to provide a write(const char* buf, size_t count) function that performs the actual write to the device, as well as a struct device* for resource management. Signed-off-by: Charles Perry <[email protected]> Acked-by: Xu Yilun <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xu Yilun <[email protected]>
2023-07-23fpga: add configuration for the FPGA KUnit test suites.Marco Pagani1-0/+2
Add configuration for the KUnit test suites for the core components of the FPGA subsystem. Signed-off-by: Marco Pagani <[email protected]> Acked-by: Xu Yilun <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xu Yilun <[email protected]>
2023-01-27mfd: intel-m10-bmc: Split into core and spi specific partsIlpo Järvinen1-1/+1
Split the common code from intel-m10-bmc driver into intel-m10-bmc-core and move the SPI bus parts into an interface specific file. intel-m10-bmc-core becomes the core MFD functions which can support multiple bus interface like SPI bus. Co-developed-by: Tianfei zhang <[email protected]> Signed-off-by: Tianfei zhang <[email protected]> Reviewed-by: Russ Weight <[email protected]> Acked-by: Guenter Roeck <[email protected]> # hwmon Reviewed-by: Xu Yilun <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]> Signed-off-by: Lee Jones <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-16Merge tag 'char-misc-6.2-rc1' of ↵Linus Torvalds1-0/+11
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char/misc driver updates from Greg KH: "Here is the large set of char/misc and other driver subsystem changes for 6.2-rc1. Nothing earth-shattering in here at all, just a lot of new driver development and minor fixes. Highlights include: - fastrpc driver updates - iio new drivers and updates - habanalabs driver updates for new hardware and features - slimbus driver updates - speakup module parameters added to aid in boot time configuration - i2c probe_new conversions for lots of different drivers - other small driver fixes and additions One semi-interesting change in here is the increase of the number of misc dynamic minors available to 1048448 to handle new huge-cpu systems. All of these have been in linux-next for a while with no reported problems" * tag 'char-misc-6.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (521 commits) extcon: usbc-tusb320: Convert to i2c's .probe_new() extcon: rt8973: Convert to i2c's .probe_new() extcon: fsa9480: Convert to i2c's .probe_new() extcon: max77843: Replace irqchip mask_invert with unmask_base chardev: fix error handling in cdev_device_add() mcb: mcb-parse: fix error handing in chameleon_parse_gdd() drivers: mcb: fix resource leak in mcb_probe() coresight: etm4x: fix repeated words in comments coresight: cti: Fix null pointer error on CTI init before ETM coresight: trbe: remove cpuhp instance node before remove cpuhp state counter: stm32-lptimer-cnt: fix the check on arr and cmp registers update misc: fastrpc: Add dma_mask to fastrpc_channel_ctx misc: fastrpc: Add mmap request assigning for static PD pool misc: fastrpc: Safekeep mmaps on interrupted invoke misc: fastrpc: Add support for audiopd misc: fastrpc: Rework fastrpc_req_munmap misc: fastrpc: Use fastrpc_map_put in fastrpc_map_create on fail misc: fastrpc: Add fastrpc_remote_heap_alloc misc: fastrpc: Add reserved mem support misc: fastrpc: Rename audio protection domain to root ...
2022-11-15fpga: m10bmc-sec: Fix kconfig dependenciesRuss Weight1-1/+3
The secure update driver depends on the firmware-upload functionality of the firmware-loader. The firmware-loader is carried in the firmware-class driver which is enabled with the tristate CONFIG_FW_LOADER option. The firmware-upload functionality is included in the firmware-class driver if the bool FW_UPLOAD config is set. The current dependency statement, "depends on FW_UPLOAD", is not adequate because it does not implicitly turn on FW_LOADER. Instead of adding a dependency, follow the convention used by drivers that require the FW_LOADER_USER_HELPER functionality of the firmware-loader by using select for both FW_LOADER and FW_UPLOAD. Fixes: bdf86d0e6ca3 ("fpga: m10bmc-sec: create max10 bmc secure update") Reported-by: kernel test robot <[email protected]> Cc: [email protected] Signed-off-by: Russ Weight <[email protected]> Acked-by: Randy Dunlap <[email protected]> Acked-by: Xu Yilun <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xu Yilun <[email protected]>
2022-10-25fpga: lattice-sysconfig-spi: add Lattice sysCONFIG FPGA managerIvan Bornyakov1-0/+11
Add support to the FPGA manager for programming Lattice ECP5 FPGA over slave SPI sysCONFIG interface. sysCONFIG interface core functionality is separate from both ECP5 and SPI specifics, so support for other FPGAs with different port types can be added in the future. Signed-off-by: Ivan Bornyakov <[email protected]> Acked-by: Xu Yilun <[email protected]> Link: https://lore.kernel.org/r/[email protected] [[email protected]: remove redundant blank line after kmemdup] Signed-off-by: Xu Yilun <[email protected]>
2022-06-24fpga: microchip-spi: add Microchip MPF FPGA managerIvan Bornyakov1-0/+8
Add support to the FPGA manager for programming Microchip Polarfire FPGAs over slave SPI interface with .dat formatted bitsream image. Signed-off-by: Ivan Bornyakov <[email protected]> Reviewed-by: Conor Dooley <[email protected]> Tested-by: Conor Dooley <[email protected]> Acked-by: Xu Yilun <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xu Yilun <[email protected]>
2022-06-08fpga: m10bmc-sec: create max10 bmc secure updateRuss Weight1-0/+12
Create a sub-driver for the FPGA Card BMC in order to support secure updates. This patch creates the Max10 BMC Secure Update driver and provides sysfs files for displaying the root entry hashes (REH) for the FPGA static region (SR), the FPGA Partial Reconfiguration (PR) region, and the card BMC. The Intel MAX10 BMC Root of Trust (RoT) requires that all BMC Nios firmware and FPGA images are authenticated using ECDSA before loading and executing on the card. Code Signing Keys (CSK) are used to sign images. CSKs are signed by a root key. The root entry hash is created from the root public key. The RoT provides authentication by storing an REH bitstream to a write-once location. Image signatures are verified against the hash. Reviewed-by: Tom Rix <[email protected]> Tested-by: Tianfei Zhang <[email protected]> Signed-off-by: Russ Weight <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xu Yilun <[email protected]>
2021-08-05Merge tag 'fpga-for-5.15' of ↵Greg Kroah-Hartman1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga into char-misc-next Moritz writes: FPGA Manager changes for 5.15-rc1 FPGA Manager - Colin's change is a simple spelling cleanup. DFL - Martin's fist change exposes DFL feature revision to client drivers - Martin's second change modifies a SPI driver to populate different spi_board_info modaliases based on the DFL feature revision All patches have been reviewed on the mailing list, and have been in the last few linux-next releases (as part of my for-next branch) without issues. Signed-off-by: Moritz Fischer <[email protected]> * tag 'fpga-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga: spi: spi-altera-dfl: support n5010 feature revision fpga: dfl: expose feature revision from struct dfl_device fpga: Fix spelling mistake "eXchnage" -> "exchange" in Kconfig
2021-07-29fpga: Fix spelling mistake "eXchnage" -> "exchange" in KconfigColin Ian King1-1/+1
There is a spelling mistake in the Kconfig text. Fix it. Reviewed-by: Tom Rix <[email protected]> Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Moritz Fischer <[email protected]>
2021-07-21fpga: versal-fpga: Add versal fpga manager driverNava kishore Manne1-0/+9
Add support for Xilinx Versal FPGA manager. PDI source type can be DDR, OCM, QSPI flash etc.. But driver allocates memory always from DDR, Since driver supports only DDR source type. Reviewed-by: Moritz Fischer <[email protected]> Signed-off-by: Appana Durga Kedareswara rao <[email protected]> Signed-off-by: Nava kishore Manne <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-06-09fpga: change FPGA indirect article to anTom Rix1-2/+2
Change use of 'a fpga' to 'an fpga' Signed-off-by: Tom Rix <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-04-26Merge tag 'arm-drivers-5.13' of ↵Linus Torvalds1-4/+4
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "Updates for SoC specific drivers include a few subsystems that have their own maintainers but send them through the soc tree: TEE/OP-TEE: - Add tracepoints around calls to secure world Memory controller drivers: - Minor fixes for Renesas, Exynos, Mediatek and Tegra platforms - Add debug statistics to Tegra20 memory controller - Update Tegra bindings and convert to dtschema ARM SCMI Firmware: - Support for modular SCMI protocols and vendor specific extensions - New SCMI IIO driver - Per-cpu DVFS The other driver changes are all from the platform maintainers directly and reflect the drivers that don't fit into any other subsystem as well as treewide changes for a particular platform. SoCFPGA: - Various cleanups contributed by Krzysztof Kozlowski Mediatek: - add MT8183 support to mutex driver - MMSYS: use per SoC array to describe the possible routing - add MMSYS support for MT8183 and MT8167 - add support for PMIC wrapper with integrated arbiter - add support for MT8192/MT6873 Tegra: - Bug fixes to PMC and clock drivers NXP/i.MX: - Update SCU power domain driver to keep console domain power on. - Add missing ADC1 power domain to SCU power domain driver. - Update comments for single global power domain in SCU power domain driver. - Add i.MX51/i.MX53 unique id support to i.MX SoC driver. NXP/FSL SoC driver updates for v5.13 - Add ACPI support for RCPM driver - Use generic io{read,write} for QE drivers after performance optimized for PowerPC - Fix QBMAN probe to cleanup HW states correctly for kexec - Various cleanup and style fix for QBMAN/QE/GUTS drivers OMAP: - Preparation to use devicetree for genpd - ti-sysc needs iorange check improved when the interconnect target module has no control registers listed - ti-sysc needs to probe l4_wkup and l4_cfg interconnects first to avoid issues with missing resources and unnecessary deferred probe - ti-sysc debug option can now detect more devices - ti-sysc now warns if an old incomplete devicetree data is found as we now rely on it being complete for am3 and 4 - soc init code needs to check for prcm and prm nodes for omap4/5 and dra7 - omap-prm driver needs to enable autoidle retention support for omap4 - omap5 clocks are missing gpmc and ocmc clock registers - pci-dra7xx now needs to use builtin_platform_driver instead of using builtin_platform_driver_probe for deferred probe to work Raspberry Pi: - Fix-up all RPi firmware drivers so as for unbind to happen in an orderly fashion - Support for RPi's PoE hat PWM bus Qualcomm - Improved detection for SCM calling conventions - Support for OEM specific wifi firmware path - Added drivers for SC7280/SM8350: RPMH, LLCC< AOSS QMP" * tag 'arm-drivers-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (165 commits) soc: aspeed: fix a ternary sign expansion bug memory: mtk-smi: Add device-link between smi-larb and smi-common memory: samsung: exynos5422-dmc: handle clk_set_parent() failure memory: renesas-rpc-if: fix possible NULL pointer dereference of resource clk: socfpga: fix iomem pointer cast on 64-bit soc: aspeed: Adapt to new LPC device tree layout pinctrl: aspeed-g5: Adapt to new LPC device tree layout ipmi: kcs: aspeed: Adapt to new LPC DTS layout ARM: dts: Remove LPC BMC and Host partitions dt-bindings: aspeed-lpc: Remove LPC partitioning soc: fsl: enable acpi support in RCPM driver soc: qcom: mdt_loader: Detect truncated read of segments soc: qcom: mdt_loader: Validate that p_filesz < p_memsz soc: qcom: pdr: Fix error return code in pdr_register_listener firmware: qcom_scm: Fix kernel-doc function names to match firmware: qcom_scm: Suppress sysfs bind attributes firmware: qcom_scm: Workaround lack of "is available" call on SC7180 firmware: qcom_scm: Reduce locking section for __get_convention() firmware: qcom_scm: Make __qcom_scm_is_call_available() return bool Revert "soc: fsl: qe: introduce qe_io{read,write}* wrappers" ...
2021-03-24fpga: Add support for Xilinx DFX AXI Shutdown managerNava kishore Manne1-1/+8
This patch adds support for Xilinx Dynamic Function eXchange(DFX) AXI shutdown manager IP. It can be used to safely handling the AXI traffic on a Reconfigurable Partition when it is undergoing dynamic reconfiguration and there by preventing system deadlock that may occur if AXI transactions are interrupted during reconfiguration. PR-Decoupler and AXI shutdown manager are completely different IPs. But both the IP registers are compatible and also both belong to the same sub-system (fpga-bridge).So using same driver for both IP's. Signed-off-by: Nava kishore Manne <[email protected]> Reviewed-by: Tom Rix <[email protected]> Signed-off-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-03-23fpga: altera: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCsKrzysztof Kozlowski1-3/+3
ARCH_SOCFPGA is being renamed to ARCH_INTEL_SOCFPGA so adjust the 32-bit ARM drivers to rely on new symbol. Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Dinh Nguyen <[email protected]>
2021-03-23arm64: socfpga: merge Agilex and N5X into ARCH_INTEL_SOCFPGAKrzysztof Kozlowski1-1/+1
Agilex, N5X and Stratix 10 share all quite similar arm64 hard cores and SoC-part. Up to a point that N5X uses the same DTSI as Agilex. From the Linux kernel point of view these are flavors of the same architecture so there is no need for three top-level arm64 architectures. Simplify this by merging all three architectures into ARCH_INTEL_SOCFPGA and dropping the other ARCH* arm64 Kconfig entries. The side effect is that the INTEL_STRATIX10_SERVICE will now be available for both 32-bit and 64-bit Intel SoCFPGA, even though it is used only for 64-bit. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Dinh Nguyen <[email protected]>
2021-01-07fpga: dfl: add support for N3000 Nios private featureXu Yilun1-0/+11
This patch adds support for the Nios handshake private feature on Intel PAC (Programmable Acceleration Card) N3000. The Nios is the embedded processor on the FPGA card. This private feature provides a handshake interface to FPGA Nios firmware, which receives retimer configuration command from host and executes via an internal SPI master (spi-altera). When Nios finishes the configuration, host takes over the ownership of the SPI master to control an Intel MAX10 BMC (Board Management Controller) Chip on the SPI bus. For Nios firmware handshake part, this driver requests the retimer configuration for Nios firmware on probe, and adds some sysfs nodes for user to query the onboard retimer's working mode and Nios firmware version. For SPI part, this driver adds a spi-altera platform device as well as the MAX10 BMC spi slave info. A spi-altera driver will be matched to handle the following SPI work. [[email protected]: Fixed up ABI doc kernel release] Reviewed-by: Tom Rix <[email protected]> Signed-off-by: Xu Yilun <[email protected]> Signed-off-by: Wu Hao <[email protected]> Signed-off-by: Matthew Gerlach <[email protected]> Signed-off-by: Russ Weight <[email protected]> Signed-off-by: YueHaibing <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-12-01fpga: Specify HAS_IOMEM dependency for FPGA_DFLDavid Gow1-0/+1
Because dfl.c uses the 'devm_ioremap', 'devm_iounmap', 'devm_ioremap_resource', and 'devm_platform_ioremap_resource' functions, it should depend on HAS_IOMEM. This fixes make allyesconfig under UML (ARCH=um), which doesn't provide HAS_IOMEM. [[email protected]: Removed "drivers: " in commit message] Fixes: 89eb35e810a8 ("fpga: dfl: map feature mmio resources in their own feature drivers") Signed-off-by: David Gow <[email protected]> Signed-off-by: Moritz Fischer <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-06-26Merge tag 'fpga-fixes-for-5.8' of ↵Greg Kroah-Hartman1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga into char-misc-next FPGA Manager fixes for 5.8-rc1 Here is one (late) fix for 5.8-rc1 merge window. Arnd's change addresses a missing build dependency. All patches have been reviewed on the mailing list, and have been in the last few linux-next releases (as part of my fixes branch) without issues. Signed-off-by: Moritz Fischer <[email protected]> * tag 'fpga-fixes-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga: fpga: zynqmp: fix modular build
2020-06-09fpga: zynqmp: fix modular buildArnd Bergmann1-1/+1
Two symbols need to be exported to allow the zynqmp-fpga module to get loaded dynamically: ERROR: modpost: "zynqmp_pm_fpga_load" [drivers/fpga/zynqmp-fpga.ko] undefined! ERROR: modpost: "zynqmp_pm_fpga_get_status" [drivers/fpga/zynqmp-fpga.ko] undefined! To ensure this is done correctly, also fix the Kconfig dependency to only allow building the fpga driver when the firmware driver is either disabled, or when it is reachable. With that, the dependency on the SoC itself can be removed, and there are no surprises when the fpga driver is built-in but the firmware a module. Fixes: 4db8180ffe7c ("firmware: xilinx: Remove eemi ops for fpga related APIs") Signed-off-by: Arnd Bergmann <[email protected]> Signed-off-by: Moritz Fischer <[email protected]>
2020-04-28fpga: dfl: fme: add performance reporting supportWu Hao1-1/+1
This patch adds support for performance reporting private feature for FPGA Management Engine (FME). Now it supports several different performance counters, including 'basic', 'cache', 'fabric', 'vtd' and 'vtd_sip'. It allows user to use standard linux tools to access these performance counters. e.g. List all events by "perf list" perf list | grep fme dfl_fme0/cache_read_hit/ [Kernel PMU event] dfl_fme0/cache_read_miss/ [Kernel PMU event] ... dfl_fme0/fab_mmio_read/ [Kernel PMU event] dfl_fme0/fab_mmio_write/ [Kernel PMU event] ... dfl_fme0/fab_port_mmio_read,portid=?/ [Kernel PMU event] dfl_fme0/fab_port_mmio_write,portid=?/ [Kernel PMU event] ... dfl_fme0/vtd_port_devtlb_1g_fill,portid=?/ [Kernel PMU event] dfl_fme0/vtd_port_devtlb_2m_fill,portid=?/ [Kernel PMU event] ... dfl_fme0/vtd_sip_iotlb_1g_hit/ [Kernel PMU event] dfl_fme0/vtd_sip_iotlb_1g_miss/ [Kernel PMU event] ... dfl_fme0/clock [Kernel PMU event] ... e.g. check increased counter value after run one application using "perf stat" command. perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_mmio_write/ ./test Performance counter stats for './test': 1 dfl_fme0/fab_mmio_read/ 2 dfl_fme0/fab_mmio_write/ 1.009496520 seconds time elapsed Please note that fabric counters support both fab_* and fab_port_*, but actually they are sharing one set of performance counters in hardware. If user wants to monitor overall data events on fab_* then fab_port_* can't be supported at the same time, see example below: perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_port_mmio_write,portid=0/ Performance counter stats for 'system wide': 0 dfl_fme0/fab_mmio_read/ <not supported> dfl_fme0/fab_port_mmio_write,portid=0/ 2.141064085 seconds time elapsed Signed-off-by: Luwei Kang <[email protected]> Signed-off-by: Xu Yilun <[email protected]> Signed-off-by: Wu Hao <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-10-16fpga: dfl: fme: add thermal management supportWu Hao1-1/+1
This patch adds support to thermal management private feature for DFL FPGA Management Engine (FME). This private feature driver registers a hwmon for thermal/temperature monitoring (hwmon temp1_input). If hardware automatic throttling is supported by this hardware, then driver also exposes sysfs interfaces under hwmon for thresholds (temp1_max/ crit/ emergency), threshold alarms (temp1_max_alarm/ temp1_crit_alarm) and throttling policy (temp1_max_policy). Signed-off-by: Luwei Kang <[email protected]> Signed-off-by: Russ Weight <[email protected]> Signed-off-by: Xu Yilun <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Guenter Roeck <[email protected]> Reviewed-by: Moritz Fischer <[email protected]> Signed-off-by: Moritz Fischer <[email protected]>
2019-09-03Merge tag 'fpga-cvp-for-5.4' of ↵Greg Kroah-Hartman1-3/+3
git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga into char-misc-next Moritz writes: FPGA Manager changes for 5.4-rc1 Here is the second set of changes for the 5.4 merge window. This patchset adds support for the v2 revision of Intel (Altera)'s CVP parts including the Stratix 10. All of this patches have been reviewed and been in the last few linux-next releases without issues. Signed-off-by: Moritz Fischer <[email protected]> * tag 'fpga-cvp-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga: fpga: altera-cvp: Add Stratix10 (V2) Support fpga: altera-cvp: Preparation for V2 parts. fpga: altera-cvp: Discover Vendor Specific offset
2019-08-24fpga: altera-cvp: Add Stratix10 (V2) SupportThor Thayer1-3/+3
Add Stratix10 specific functions that use a credit mechanism to throttle data to the CvP FIFOs. Add a private structure with function pointers for V1 vs V2 functions. Signed-off-by: Thor Thayer <[email protected]> Signed-off-by: Moritz Fischer <[email protected]>
2019-07-24fpga-manager: altera-ps-spi: Fix build errorYueHaibing1-0/+1
If BITREVERSE is m and FPGA_MGR_ALTERA_PS_SPI is y, build fails: drivers/fpga/altera-ps-spi.o: In function `altera_ps_write': altera-ps-spi.c:(.text+0x4ec): undefined reference to `byte_rev_table' Select BITREVERSE to fix this. Reported-by: Hulk Robot <[email protected]> Fixes: fcfe18f885f6 ("fpga-manager: altera-ps-spi: use bitrev8x4") Signed-off-by: YueHaibing <[email protected]> Cc: stable <[email protected]> Acked-by: Moritz Fischer <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-06-20drivers: fpga: Kconfig: pedantic cleanupsEnrico Weigelt1-3/+3
Formatting of Kconfig files doesn't look so pretty, so just take damp cloth and clean it up. Signed-off-by: Enrico Weigelt <[email protected]> Signed-off-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner1-0/+1
Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-04-15fpga manager: Adding FPGA Manager support for Xilinx zynqmpNava kishore Manne1-0/+9
This patch adds FPGA Manager support for the Xilinx ZynqMP chip. Signed-off-by: Nava kishore Manne <[email protected]> Reviewed-by: Moritz Fischer <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2019-01-31fpga: altera_freeze_bridge: remove restriction to socfpgaAlan Tull1-1/+1
The Altera Freeze Bridge should not be restricted to ARCH_SOCFPGA since it can be used on other platforms such as Stratix10. Signed-off-by: Alan Tull <[email protected]> Reviewed-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-11-26fpga: add intel stratix10 soc fpga manager driverAlan Tull1-0/+6
Add driver for reconfiguring Intel Stratix10 SoC FPGA devices. This driver communicates through the Intel service layer driver which does communication with privileged hardware (that does the FPGA programming) through a secure mailbox. Signed-off-by: Alan Tull <[email protected]> Signed-off-by: Richard Gong <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl: add FPGA Accelerated Function Unit driver basic frameworkWu Hao1-0/+9
On DFL FPGA devices, the Accelerated Function Unit (AFU), can be reprogrammed for different functions. It connects to the FPGA infrastructure (static FPGA region) via a Port. Port CSRs are implemented separately from the AFU CSRs to provide control and status of the Port. Once valid PR bitstream is programmed into the AFU, it allows access to the AFU CSRs in the AFU MMIO space. This patch only implements basic driver framework for AFU, including device file operation framework. Signed-off-by: Tim Whisonant <[email protected]> Signed-off-by: Enno Luebbers <[email protected]> Signed-off-by: Shiva Rao <[email protected]> Signed-off-by: Christopher Rauer <[email protected]> Signed-off-by: Xiao Guangrong <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl: add fpga region platform driver for FMEWu Hao1-0/+6
This patch adds fpga region platform driver for FPGA Management Engine. It register an fpga region with given fpga manager / bridge device. Signed-off-by: Tim Whisonant <[email protected]> Signed-off-by: Enno Luebbers <[email protected]> Signed-off-by: Shiva Rao <[email protected]> Signed-off-by: Christopher Rauer <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl: add fpga bridge platform driver for FMEWu Hao1-0/+6
This patch adds fpga bridge platform driver for FPGA Management Engine. It implements the enable_set callback for fpga bridge. Signed-off-by: Tim Whisonant <[email protected]> Signed-off-by: Enno Luebbers <[email protected]> Signed-off-by: Shiva Rao <[email protected]> Signed-off-by: Christopher Rauer <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl: add fpga manager platform driver for FMEWu Hao1-0/+6
This patch adds fpga manager driver for FPGA Management Engine (FME). It implements fpga_manager_ops for FPGA Partial Reconfiguration function. Signed-off-by: Tim Whisonant <[email protected]> Signed-off-by: Enno Luebbers <[email protected]> Signed-off-by: Shiva Rao <[email protected]> Signed-off-by: Christopher Rauer <[email protected]> Signed-off-by: Kang Luwei <[email protected]> Signed-off-by: Xiao Guangrong <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl: add FPGA Management Engine driver basic frameworkKang Luwei1-0/+10
The FPGA Management Engine (FME) provides power, thermal management, performance counters, partial reconfiguration and other functions. For each function, it is packaged into a private feature linked to the FME feature device in the 'Device Feature List'. It's a platform device created by DFL framework. This patch adds the basic framework of FME platform driver. It defines sub feature drivers to handle the different sub features, including init, uinit and ioctl. It also registers the file operations for the device file. Signed-off-by: Tim Whisonant <[email protected]> Signed-off-by: Enno Luebbers <[email protected]> Signed-off-by: Shiva Rao <[email protected]> Signed-off-by: Christopher Rauer <[email protected]> Signed-off-by: Kang Luwei <[email protected]> Signed-off-by: Xiao Guangrong <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: add FPGA DFL PCIe device driverZhang Yi1-0/+15
This patch implements the basic framework of the driver for FPGA PCIe device which implements the Device Feature List (DFL) in its MMIO space. This driver is verified on Intel(R) PCIe-based FPGA DFL devices, including both integrated (e.g. Intel Server Platform with In-package FPGA) and discrete (e.g. Intel FPGA PCIe Acceleration Cards) solutions. Signed-off-by: Tim Whisonant <[email protected]> Signed-off-by: Enno Luebbers <[email protected]> Signed-off-by: Shiva Rao <[email protected]> Signed-off-by: Christopher Rauer <[email protected]> Signed-off-by: Zhang Yi <[email protected]> Signed-off-by: Xiao Guangrong <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: add device feature list supportWu Hao1-0/+16
Device Feature List (DFL) defines a feature list structure that creates a linked list of feature headers within the MMIO space to provide an extensible way of adding features. This patch introduces a kernel module to provide basic infrastructure to support FPGA devices which implement the Device Feature List. Usually there will be different features and their sub features linked into the DFL. This code provides common APIs for feature enumeration, it creates a container device (FPGA base region), walks through the DFLs and creates platform devices for feature devices (Currently it only supports two different feature devices, FPGA Management Engine (FME) and Port which the Accelerator Function Unit (AFU) connected to). In order to enumerate the DFLs, the common APIs required low level driver to provide necessary enumeration information (e.g. address for each device feature list for given device) and fill it to the dfl_fpga_enum_info data structure. Please refer to below description for APIs added for enumeration. Functions for enumeration information preparation: *dfl_fpga_enum_info_alloc allocate enumeration information data structure. *dfl_fpga_enum_info_add_dfl add a device feature list to dfl_fpga_enum_info data structure. *dfl_fpga_enum_info_free free dfl_fpga_enum_info data structure and related resources. Functions for feature device enumeration: *dfl_fpga_feature_devs_enumerate enumerate feature devices and return container device. *dfl_fpga_feature_devs_remove remove feature devices under given container device. Signed-off-by: Tim Whisonant <[email protected]> Signed-off-by: Enno Luebbers <[email protected]> Signed-off-by: Shiva Rao <[email protected]> Signed-off-by: Christopher Rauer <[email protected]> Signed-off-by: Zhang Yi <[email protected]> Signed-off-by: Xiao Guangrong <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-04-23fpga: lattice machxo2: Add Lattice MachXO2 supportPaolo Pisati1-0/+7
This patch adds support to the FPGA manager for programming MachXO2 device’s internal flash memory, via slave SPI. Signed-off-by: Paolo Pisati <[email protected]> [[email protected]: use existing FPGA mgr API] Signed-off-by: Alan Tull <[email protected]> Signed-off-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-04-23fpga: Remove depends on HAS_DMA in case of platform dependencyGeert Uytterhoeven1-1/+0
Remove dependencies on HAS_DMA where a Kconfig symbol depends on another symbol that implies HAS_DMA, and, optionally, on "|| COMPILE_TEST". In most cases this other symbol is an architecture or platform specific symbol, or PCI. Generic symbols and drivers without platform dependencies keep their dependencies on HAS_DMA, to prevent compiling subsystems or drivers that cannot work anyway. This simplifies the dependencies, and allows to improve compile-testing. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Mark Brown <[email protected]> Acked-by: Robin Murphy <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-11-28fpga: clean up fpga KconfigAlan Tull1-54/+54
The fpga menuconfig has gotten messy. The bridges and managers are mixed together. * Separate the bridges and things dependent on CONFIG_FPGA_BRIDGE from the managers. * Group the managers by vendor in order that they were added to the kernel. The following is what the menuconfig ends up looking like more or less (platform dependencies are hiding some of these on any given platform). --- FPGA Configuration Framework <*> Altera SOCFPGA FPGA Manager <*> Altera SoCFPGA Arria10 <*> Altera Partial Reconfiguration IP Core <*> Platform support of Altera Partial Reconfiguration IP Core <*> Altera FPGA Passive Serial over SPI <*> Altera Arria-V/Cyclone-V/Stratix-V CvP FPGA Manager <*> Xilinx Zynq FPGA <*> Xilinx Configuration over Slave Serial (SPI) <*> Lattice iCE40 SPI <*> Technologic Systems TS-73xx SBC FPGA Manager <*> FPGA Bridge Framework <*> Altera SoCFPGA FPGA Bridges <*> Altera FPGA Freeze Bridge <*> Xilinx LogiCORE PR Decoupler <*> FPGA Region <*> FPGA Region Device Tree Overlay Support Signed-off-by: Alan Tull <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-11-28fpga: region: move device tree support to of-fpga-region.cAlan Tull1-4/+11
Create of-fpga-region.c and move the following functions without modification from fpga-region.c. * of_fpga_region_find * of_fpga_region_get_mgr * of_fpga_region_get_bridges * child_regions_with_firmware * of_fpga_region_parse_ov * of_fpga_region_notify_pre_apply * of_fpga_region_notify_post_remove * of_fpga_region_notify * of_fpga_region_probe * of_fpga_region_remove Create two new functions with some code from fpga_region_init/exit. * of_fpga_region_init * of_fpga_region_exit Signed-off-by: Alan Tull <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-07-17fpga manager: Add Altera CvP driverAnatolij Gustschin1-0/+7
Add FPGA manager driver for loading Arria-V/Cyclone-V/Stratix-V and Arria-10 FPGAs via CvP. Signed-off-by: Anatolij Gustschin <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Signed-off-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-07-17fpga manager: Add altera-ps-spi driver for Altera FPGAsJoshua Clayton1-0/+7
altera-ps-spi loads FPGA firmware over SPI, using the "passive serial" interface on Altera Arria 10, Cyclone V or Stratix V FPGAs. This is one of the simpler ways to set up an FPGA at runtime. The signal interface is close to unidirectional SPI with lsb first. Signed-off-by: Joshua Clayton <[email protected]> Signed-off-by: Anatolij Gustschin <[email protected]> Signed-off-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-07-17Make FPGA a menuconfig to ease disabling it allVincent Legoll1-5/+1
No need to get into the submenu to disable all FPGA-related config entries Signed-off-by: Vincent Legoll <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-04-08fpga: Add support for Xilinx LogiCORE PR DecouplerMoritz Fischer1-0/+10
This adds support for the Xilinx LogiCORE PR Decoupler soft-ip that does decoupling of PR regions in the FPGA fabric during partial reconfiguration. Signed-off-by: Moritz Fischer <[email protected]> Signed-off-by: Michal Simek <[email protected]> Cc: Sören Brinkmann <[email protected]> Cc: [email protected] Cc: [email protected] Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-04-08fpga pr ip: Platform driver for Altera Partial Reconfiguration IP.Matthew Gerlach1-0/+7
This adds a platform bus driver for a fpga-mgr driver that uses the Altera Partial Reconfiguration IP component. Signed-off-by: Matthew Gerlach <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-04-08fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.Matthew Gerlach1-0/+5
Adding the core functions necessary for a fpga-mgr driver for the Altera Partial IP component. It is intended for these functions to be used by the various bus implementations like the platform bus or the PCIe bus. Signed-off-by: Matthew Gerlach <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-04-08fpga manager: Add Xilinx slave serial SPI driverAnatolij Gustschin1-0/+7
The driver loads FPGA firmware over SPI, using the "slave serial" configuration interface on Xilinx FPGAs. Signed-off-by: Anatolij Gustschin <[email protected]> Acked-by: Michal Simek <[email protected]> Reviewed-by: Moritz Fischer <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-03-17fpga: Add support for Lattice iCE40 FPGAsJoel Holdsworth1-0/+6
This patch adds support to the FPGA manager for configuring the SRAM of iCE40LM, iCE40LP, iCE40HX, iCE40 Ultra, iCE40 UltraLite and iCE40 UltraPlus devices, through slave SPI. Signed-off-by: Joel Holdsworth <[email protected]> Reviewed-by: Marek Vasut <[email protected]> Reviewed-by: Moritz Fischer <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
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