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path: root/drivers/cxl
AgeCommit message (Expand)AuthorFilesLines
2023-02-10cxl/region: Add volatile region creation supportDan Williams3-14/+72
2023-02-10cxl/region: Validate region mode vs decoder modeDan Williams1-0/+6
2023-02-10cxl/region: Support empty uuids for non-pmem regionsDan Williams1-2/+9
2023-02-10cxl/region: Add a mode attribute for regionsDan Williams3-11/+25
2023-02-10cxl/memdev: Fix endpoint port removalDan Williams3-26/+35
2023-02-09cxl/mem: Correct full ID range allocationDavidlohr Bueso1-1/+1
2023-02-07Merge branch 'for-6.3/cxl-events' into cxl/nextDan Williams6-1/+1141
2023-02-07Merge branch 'for-6.3/cxl' into cxl/nextDan Williams12-126/+313
2023-02-07cxl/region: Fix passthrough-decoder detectionDan Williams1-2/+2
2023-02-06cxl/region: Fix null pointer dereference for resetting decoderFan Ni1-3/+5
2023-01-30cxl/pci: Fix irq oneshot expectationsDan Williams1-1/+2
2023-01-30cxl/pci: Set the device timestampJonathan Cameron3-0/+40
2023-01-30cxl/mbox: Add missing parameter to docs.Jonathan Cameron1-0/+1
2023-01-27cxl/mbox: Fix Payload Length check for Get Log commandRobert Richter1-3/+22
2023-01-27driver core: make struct bus_type.uevent() take a const *Greg Kroah-Hartman4-8/+8
2023-01-27driver core: make struct device_type.devnode() take a const *Greg Kroah-Hartman1-1/+1
2023-01-26cxl/mem: Trace Memory Module Event RecordIra Weiny3-0/+182
2023-01-26cxl/mem: Trace DRAM Event RecordIra Weiny3-0/+127
2023-01-26cxl/mem: Trace General Media Event RecordIra Weiny3-2/+170
2023-01-26cxl/mem: Wire up event interruptsDavidlohr Bueso4-10/+240
2023-01-26cxl: fix spelling mistakesRandy Dunlap4-4/+4
2023-01-26cxl/mbox: Add debug messages for enabled mailbox commandsRobert Richter1-1/+2
2023-01-26cxl/mem: Read, trace, and clear events on driver loadIra Weiny5-1/+392
2023-01-25cxl/pmem: Fix nvdimm unregistration when cxl_pmem driver is absentDan Williams3-39/+28
2023-01-25cxl/port: Link the 'parent_dport' in portX/ and endpointX/ sysfsDan Williams1-0/+29
2023-01-25cxl/region: Clarify when a cxld->commit() callback is mandatoryDan Williams1-2/+17
2023-01-24cxl/pci: Show opcode in debug messages when sending a commandRobert Richter1-1/+1
2023-01-09cxl: fix cxl_report_and_clear() RAS UE addr mis-assignmentDave Jiang1-2/+5
2023-01-05cxl/region: Only warn about cpu_cache_invalidate_memregion() onceDavidlohr Bueso1-1/+1
2023-01-04cxl/pci: Move tracepoint definitions to drivers/cxl/core/Dan Williams7-111/+234
2022-12-08cxl/region: Fix memdev reuse checkFan Ni1-1/+1
2022-12-06cxl/pci: Remove endian confusionDan Williams1-4/+3
2022-12-06cxl/pci: Add some type-safety to the AER trace pointsDan Williams1-2/+2
2022-12-06cxl/security: Drop security command ioctl uapiDan Williams1-17/+0
2022-12-06cxl/mbox: Add variable output size validation for internal commandsDan Williams2-9/+16
2022-12-06cxl/mbox: Enable cxl_mbox_send_cmd() users to validate output sizeDan Williams4-62/+126
2022-12-06cxl/security: Fix Get Security State output payload endian handlingDan Williams1-1/+5
2022-12-05cxl: update names for interleave ways conversion macrosDave Jiang4-16/+16
2022-12-05cxl: update names for interleave granularity conversion macrosDave Jiang4-14/+15
2022-12-05cxl/acpi: Warn about an invalid CHBCR in an existing CHBS entryRobert Richter1-1/+2
2022-12-05cxl/acpi: Fail decoder add if CXIMS for HBIG is missingAlison Schofield1-0/+5
2022-12-05cxl/region: Fix spelling mistake "memergion" -> "memregion"Colin Ian King1-1/+1
2022-12-05cxl/regs: Fix sparse warningDan Williams1-1/+1
2022-12-05Merge branch 'for-6.2/cxl-xor' into for-6.2/cxlDan Williams3-8/+149
2022-12-05Merge branch 'for-6.2/cxl-aer' into for-6.2/cxlDan Williams9-149/+324
2022-12-05Merge branch 'for-6.2/cxl-security' into for-6.2/cxlDan Williams9-3/+332
2022-12-05cxl/port: Add RCD endpoint port enumerationDan Williams4-8/+44
2022-12-05cxl/mem: Move devm_cxl_add_endpoint() from cxl_core to cxl_memDan Williams5-49/+47
2022-12-03cxl/acpi: Support CXL XOR Interleave Math (CXIMS)Alison Schofield3-8/+149
2022-12-03cxl/pci: Add callback to log AER correctable errorDave Jiang1-0/+20
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