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path: root/drivers/cxl
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2023-09-22cxl/acpi: Annotate struct cxl_cxims_data with __counted_byKees Cook1-2/+2
2023-09-22cxl/port: Fix cxl_test register enumeration regressionDan Williams1-4/+9
2023-09-14cxl/region: Refactor granularity select in cxl_port_setup_targets()Alison Schofield1-9/+8
2023-09-14cxl/region: Match auto-discovered region decoders by HPA rangeAlison Schofield1-1/+23
2023-09-14cxl/mbox: Fix CEL logic for poison and security commandsIra Weiny1-11/+12
2023-09-11cxl/pci: Replace host_bridge->native_aer with pcie_aer_is_native()Smita Koralahalli1-2/+1
2023-09-11cxl/pci: Fix appropriate checking for _OSC while handling CXL RAS registersSmita Koralahalli1-3/+3
2023-07-28cxl/memdev: Only show sanitize sysfs files when supportedDavidlohr Bueso3-1/+78
2023-07-28cxl/memdev: Document security state in kern-docDavidlohr Bueso1-0/+1
2023-07-18cxl/acpi: Return 'rc' instead of '0' in cxl_parse_cfmws()Breno Leitao1-1/+1
2023-07-18cxl/acpi: Fix a use-after-free in cxl_parse_cfmws()Breno Leitao1-2/+1
2023-07-14cxl/mem: Fix a double shift bugDan Carpenter1-1/+1
2023-07-14cxl: fix CONFIG_FW_LOADER dependencyArnd Bergmann1-1/+2
2023-06-29cxl: Fix one kernel-doc commentYang Li1-1/+1
2023-06-27cxl/pci: Use correct flag for sanitize pollingDavidlohr Bueso1-1/+1
2023-06-25Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams12-291/+443
2023-06-25Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams10-7/+224
2023-06-25perf: CXL Performance Monitoring Unit driverJonathan Cameron1-0/+13
2023-06-25Merge branch 'for-6.5/cxl-region-fixes' into for-6.5/cxlDan Williams2-46/+72
2023-06-25Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxlDan Williams16-445/+515
2023-06-25Merge branch 'for-6.5/cxl-fwupd' into for-6.5/cxlDan Williams4-0/+395
2023-06-25Merge branch 'for-6.5/cxl-background' into for-6.5/cxlDan Williams6-21/+434
2023-06-25cxl: add a firmware update mechanism using the sysfs firmware loaderVishal Verma4-0/+395
2023-06-25cxl/mem: Support Secure EraseDavidlohr Bueso3-1/+34
2023-06-25cxl/mem: Wire up Sanitization supportDavidlohr Bueso4-0/+132
2023-06-25cxl/mbox: Add sanitization handling machineryDavidlohr Bueso3-3/+91
2023-06-25cxl/mem: Introduce security state sysfs fileDavidlohr Bueso3-0/+46
2023-06-25cxl/mbox: Allow for IRQ_NONE case in the isrDavidlohr Bueso1-2/+4
2023-06-25Revert "cxl/port: Enable the HDM decoder capability for switch ports"Dan Williams3-33/+9
2023-06-25cxl/memdev: Formalize endpoint port linkageDan Williams4-5/+8
2023-06-25cxl/pci: Unconditionally unmask 256B Flit errorsDan Williams1-16/+2
2023-06-25cxl/region: Manage decoder target_type at decoder-attach timeDan Williams1-0/+12
2023-06-25cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEMDan Williams2-10/+27
2023-06-25cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}Dan Williams5-12/+13
2023-06-25cxl/memdev: Make mailbox functionality optionalDan Williams3-1/+28
2023-06-25cxl/mbox: Move mailbox related driver state to its own data structureDan Williams7-271/+312
2023-06-25cxl: Remove leftover attribute documentation in 'struct cxl_dev_state'Dan Williams1-1/+0
2023-06-25cxl: Fix kernel-doc warningsDan Williams1-3/+3
2023-06-25cxl/regs: Clarify when a 'struct cxl_register_map' is input vs outputDan Williams2-6/+6
2023-06-25cxl/region: Fix state transitions after reset failureDan Williams1-11/+15
2023-06-25cxl/region: Flag partially torn down regions as unusableDan Williams2-0/+20
2023-06-25cxl/region: Move cache invalidation before region teardown, and before setupDan Williams2-36/+38
2023-06-25cxl/port: Store the downstream port's Component Register mappings in struct c...Robert Richter2-0/+13
2023-06-25cxl/port: Store the port's Component Register mappings in struct cxl_portRobert Richter2-0/+29
2023-06-25cxl/pci: Early setup RCH dport component registers from RCRBRobert Richter4-18/+57
2023-06-25cxl/mem: Prepare for early RCH dport component register setupRobert Richter1-5/+4
2023-06-25cxl/regs: Remove early capability checks in Component Register setupRobert Richter3-9/+6
2023-06-25cxl/port: Remove Component Register base address from struct cxl_dportRobert Richter2-3/+0
2023-06-25cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's portRobert Richter1-28/+63
2023-06-25cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs()Robert Richter1-45/+45
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