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path: root/drivers/cxl/pci.c
AgeCommit message (Expand)AuthorFilesLines
2023-06-27cxl/pci: Use correct flag for sanitize pollingDavidlohr Bueso1-1/+1
2023-06-25Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams1-75/+46
2023-06-25Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams1-1/+25
2023-06-25Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxlDan Williams1-93/+87
2023-06-25Merge branch 'for-6.5/cxl-fwupd' into for-6.5/cxlDan Williams1-0/+4
2023-06-25cxl: add a firmware update mechanism using the sysfs firmware loaderVishal Verma1-0/+4
2023-06-25cxl/mem: Wire up Sanitization supportDavidlohr Bueso1-0/+6
2023-06-25cxl/mbox: Add sanitization handling machineryDavidlohr Bueso1-3/+74
2023-06-25cxl/mbox: Allow for IRQ_NONE case in the isrDavidlohr Bueso1-2/+4
2023-06-25cxl/pci: Unconditionally unmask 256B Flit errorsDan Williams1-16/+2
2023-06-25cxl/mbox: Move mailbox related driver state to its own data structureDan Williams1-53/+61
2023-06-25cxl/pci: Early setup RCH dport component registers from RCRBRobert Richter1-9/+48
2023-06-25cxl/regs: Remove early capability checks in Component Register setupRobert Richter1-0/+2
2023-06-25cxl/pci: Refactor component register discovery for reuseTerry Bowman1-74/+5
2023-06-25cxl/core/regs: Add @dev to cxl_register_mapRobert Richter1-12/+11
2023-05-30cxl/pci: Find and register CXL PMU devicesJonathan Cameron1-1/+25
2023-05-23cxl/mbox: Add background cmd handling machineryDavidlohr Bueso1-0/+89
2023-05-23cxl/pci: Introduce cxl_request_irq()Davidlohr Bueso1-16/+23
2023-05-23cxl/pci: Allocate irq vectors earlier during probeDavidlohr Bueso1-4/+4
2023-05-18cxl: Move cxl_await_media_ready() to before capacity info retrievalDave Jiang1-0/+6
2023-04-23Merge branch 'for-6.4/cxl-poison' into for-6.4/cxlDan Williams1-0/+4
2023-04-23cxl/mbox: Initialize the poison stateAlison Schofield1-0/+4
2023-04-18cxl/pci: Use CDAT DOE mailbox created by PCI coreLukas Wunner1-49/+0
2023-02-14Merge branch 'for-6.3/cxl' into cxl/nextDan Williams1-8/+62
2023-02-14cxl: add RAS status unmasking for CXLDave Jiang1-0/+65
2023-02-14cxl: remove unnecessary calling of pci_enable_pcie_error_reporting()Dave Jiang1-11/+0
2023-01-30cxl/pci: Fix irq oneshot expectationsDan Williams1-1/+2
2023-01-30cxl/pci: Set the device timestampJonathan Cameron1-0/+4
2023-01-26cxl/mem: Wire up event interruptsDavidlohr Bueso1-10/+211
2023-01-26cxl/mem: Read, trace, and clear events on driver loadIra Weiny1-0/+33
2023-01-24cxl/pci: Show opcode in debug messages when sending a commandRobert Richter1-1/+1
2023-01-04cxl/pci: Move tracepoint definitions to drivers/cxl/core/Dan Williams1-111/+0
2022-12-06cxl/pci: Remove endian confusionDan Williams1-4/+3
2022-12-06cxl/pci: Add some type-safety to the AER trace pointsDan Williams1-2/+2
2022-12-05Merge branch 'for-6.2/cxl-aer' into for-6.2/cxlDan Williams1-40/+173
2022-12-05cxl/port: Add RCD endpoint port enumerationDan Williams1-0/+10
2022-12-03cxl/pci: Add callback to log AER correctable errorDave Jiang1-0/+20
2022-12-03cxl/pci: Add (hopeful) error handling supportDan Williams1-0/+137
2022-12-03cxl/pci: add tracepoint events for CXL RASDave Jiang1-0/+2
2022-12-03cxl/pci: Find and map the RAS Capability StructureDan Williams1-0/+8
2022-12-03cxl/core/regs: Make cxl_map_{component, device}_regs() device genericDan Williams1-19/+6
2022-12-03cxl/pci: Kill cxl_map_regs()Dan Williams1-22/+1
2022-12-02cxl/pmem: Refactor nvdimm device registration, delete the workqueueDan Williams1-3/+0
2022-11-14cxl/doe: Request exclusive DOE accessIra Weiny1-0/+5
2022-07-19cxl/pci: Create PCI DOE mailbox's for memory devicesIra Weiny1-0/+44
2022-07-09cxl/mem: Convert partition-info to resourcesDan Williams1-1/+1
2022-05-19cxl/mem: Consolidate CXL DVSEC Range enumeration in the coreDan Williams1-135/+0
2022-05-19cxl/pci: Move cxl_await_media_ready() to the coreDan Williams1-44/+1
2022-05-19cxl/pci: Drop wait_for_valid() from cxl_await_media_ready()Dan Williams1-4/+0
2022-05-19cxl/pci: Consolidate wait_for_media() and wait_for_media_ready()Dan Williams1-2/+2
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