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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2019-02-21clk: imx8mq: Add missing M4 clocksCarlo Caione1-0/+7
2019-02-21clk: imx: Add clock driver support for imx8mmBai Ping3-0/+682
2019-02-21clk: imx: Add PLLs driver for imx8mm socBai Ping3-1/+418
2019-02-21clk: imx5: add imx5_SCC2_IPG_GATEMichael Grzeschik1-0/+1
2019-02-21clk: imx: scu: add set parent supportAisheng Dong2-3/+100
2019-02-21clk: imx: scu: add fallback compatible string supportAisheng Dong1-0/+1
2019-02-21clk: imx8mq: Make parent names arrays const pointersAbel Vesa1-97/+97
2019-02-21clk: imx: Make parents const pointer in mux wrappersAbel Vesa1-1/+2
2019-02-21clk: imx: Make parent_names const pointer in composite-8mAbel Vesa2-2/+2
2019-02-20clk: at91: fix masterck nameAlexandre Belloni3-4/+4
2019-02-20clk: at91: fix at91sam9x5 peripheral clock numberAlexandre Belloni1-2/+1
2019-02-18clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' staticWei Yongjun1-1/+1
2019-02-15Merge tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Arnd Bergmann7-98/+913
2019-02-15clk: ti: check clock type before doing autoidle opsAndreas Kemnade1-4/+16
2019-02-15clk: ti: add a usecount for autoidleAndreas Kemnade1-4/+28
2019-02-15clk: ti: generalize the init sequence of clk_hw_omap clocksTero Kristo6-24/+31
2019-02-15clk: ti: remove usage of CLK_IS_BASICTero Kristo6-6/+6
2019-02-15clk: ti: add new API for checking if a provided clock is an OMAP clockTero Kristo2-0/+20
2019-02-15clk: ti: move clk_hw_omap list handling under generic part of the driverTero Kristo3-39/+69
2019-02-13Merge tag 'sunxi-clk-fixes-for-5.0' of https://git.kernel.org/pub/scm/linux/k...Stephen Boyd2-3/+3
2019-02-13clk: meson: meson8b: fix the naming of the APB clocksMartin Blumenstingl2-14/+14
2019-02-13clk: meson: Add G12A AO Clock + Reset ControllerNeil Armstrong4-1/+491
2019-02-06clk: clk-st: avoid clkdev lookup leak at removeMatti Vaittinen1-1/+2
2019-02-06clk: clk-max77686: Clean clkdev lookup leak and use devmMatti Vaittinen1-22/+6
2019-02-06clkdev: add managed clkdev lookup registrationMatti Vaittinen1-23/+88
2019-02-06clk: Add (devm_)clk_get_optional() functionsPhil Edworthy1-0/+11
2019-02-06clk: Add comment about __of_clk_get_by_name() error valuesPhil Edworthy1-0/+6
2019-02-06clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210Peter De Schrijver2-1/+6
2019-02-06clk: tegra: dfll: add CVB tables for Tegra210Joseph Lo2-0/+427
2019-02-06clk: tegra: dfll: round down voltages based on alignmentJoseph Lo1-8/+13
2019-02-06clk: tegra: dfll: support PWM regulator controlJoseph Lo1-67/+377
2019-02-06clk: tegra: dfll: CVB calculation alignment with the regulatorJoseph Lo4-14/+59
2019-02-06clk: tegra: dfll: registration for multiple SoCsPeter De Schrijver1-11/+34
2019-02-05clk: ingenic: jz4740: Fix gating of UDC clockPaul Cercueil1-1/+1
2019-02-05clk: mediatek: update clock driver of MT2712Weiyi Lu1-2/+6
2019-02-05clk: renesas: r8a774c0: Add TMU clockBiju Das1-0/+5
2019-02-05clk: renesas: r8a77980: Add RPC clocksSergei Shtylyov1-0/+8
2019-02-05clk: renesas: rcar-gen3: Add RPC clocksSergei Shtylyov2-0/+105
2019-02-04clk: meson: factorise meson64 peripheral clock controller driversJerome Brunet7-176/+313
2019-02-04clk: meson: g12a: add peripheral clock controllerJian Hu5-2/+2594
2019-02-04clk: meson: pll: update driver for the g12aJerome Brunet2-59/+154
2019-02-02clk: meson: rework and clean drivers dependenciesJerome Brunet29-281/+465
2019-02-02clk: meson: axg-audio does not require sysconJerome Brunet1-1/+1
2019-02-02clk: meson: use CONFIG_ARCH_MESON to enter meson clk directoryJerome Brunet1-1/+1
2019-02-02clk: export some clk_hw function symbols for module driversJerome Brunet1-0/+3
2019-02-01clk: Document and simplify clk_core_get_rate_nolock()Stephen Boyd1-15/+10
2019-02-01clk: samsung: exynos5433: Add selected IMEM clocksKamil Konieczny1-0/+32
2019-02-01clk: samsung: exynos5433: Fix name typo in sssxKamil Konieczny1-1/+1
2019-02-01clk: samsung: exynos5433: Fix definition of CLK_ACLK_IMEM_{200, 266} clocksKamil Konieczny1-2/+2
2019-01-28clk: sunxi: A31: Fix wrong AHB gate numberAndre Przywara1-2/+2