aboutsummaryrefslogtreecommitdiff
path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2019-04-12clk: imx: Fix PLL_1416X not rounding ratesLeonard Crestez1-1/+1
2019-04-12clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-typeFinley Xiao2-3/+29
2019-04-12clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288Douglas Anderson1-0/+11
2019-04-12clk: mediatek: fix clk-gate flag settingWeiyi Lu1-2/+1
2019-04-12clk: rockchip: Limit use of USB PHY clock to USB on rk3288Matthias Kaehlcke1-2/+2
2019-04-12clk: rockchip: Fix video codec clocks on rk3288Douglas Anderson1-2/+2
2019-04-11clk: ingenic: jz4725b: Add UDC PHY clockPaul Cercueil1-0/+6
2019-04-11clk: qcom: Skip halt checks on gcc_pcie_0_pipe_clk for 8998Marc Gonzalez1-1/+1
2019-04-11clk: qcom: Add QCS404 TuringCCBjorn Andersson3-0/+177
2019-04-11clk: qcom: branch: Add AON clock opsBjorn Andersson2-0/+7
2019-04-11clk: qcom: gcc-qcs404: Add CDSP related clocks and resetsBjorn Andersson1-0/+90
2019-04-11clk: mediatek: Allow changing PLL rate when it is offJames Liao1-11/+2
2019-04-11clk: mediatek: Add MT8183 clock supportWeiyi Lu15-0/+2196
2019-04-11clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_dataWeiyi Lu2-6/+12
2019-04-11clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_dataOwen Chen2-4/+13
2019-04-11clk: mediatek: Add new clkmux register APIOwen Chen3-1/+314
2019-04-11clk: mediatek: Disable tuner_en before change PLL rateOwen Chen1-14/+34
2019-04-11clk: rockchip: Make rkpwm a critical clock on rk3288Douglas Anderson1-1/+3
2019-04-11clk: ux500: add range to usleep_rangeNicholas Mc Guire1-1/+2
2019-04-11clk: tegra: Make tegra_clk_super_mux_ops staticYueHaibing1-1/+1
2019-04-11clk: davinci: cfgchip: use PTR_ERR_OR_ZERO in da8xx_cfgchip_register_div4p5Ding Xiang1-3/+1
2019-04-11clk: zynqmp: fix check for fractional clockMichael Tretter1-3/+6
2019-04-11clk: zynqmp: do not export zynqmp_clk_register_* functionsMichael Tretter2-2/+0
2019-04-11clk: zynqmp: fix kerneldoc of __zynqmp_clock_get_parentsMichael Tretter1-1/+1
2019-04-11drivers: clk: Update clock driver to handle clock attributeRajan Vaja1-13/+29
2019-04-11drivers: clk: zynqmp: Allow zero divisor valueRajan Vaja1-0/+7
2019-04-11clk: renesas: rcar-gen3: Remove unused variableStephen Boyd1-1/+0
2019-04-10clk: x86: Add system specific quirk to mark clocks as criticalDavid Müller1-3/+11
2019-04-10clk: sunxi-ng: sun5i: Export the MBUS clockMaxime Ripard1-4/+0
2019-04-09clk: sunxi-ng: a83t: Add pll-video0 as parent of csi-mclkChen-Yu Tsai1-2/+3
2019-04-08clk: meson: axg-audio: add g12a supportMaxime Jourdan2-8/+239
2019-04-08clk: meson: axg-audio: don't register inputs in the onecell dataJerome Brunet2-44/+6
2019-04-08clk: meson: axg_audio: replace prefix axg by audJerome Brunet1-482/+482
2019-04-04clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return valueTakeshi Kihara1-16/+14
2019-04-04clk: sunxi-ng: nkmp: Explain why zero width check is neededJernej Skrabec1-0/+6
2019-04-04clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rateJernej Skrabec1-3/+3
2019-04-03clk: imx5: Fix i.MX50 ESDHC clock registersJonathan Neuschäfer1-10/+30
2019-04-03clk: imx5: Fix i.MX50 mainbus clock registersJonathan Neuschäfer1-4/+15
2019-04-03clk: sunxi-ng: h6: Preset hdmi-cec clock parentJernej Skrabec1-0/+11
2019-04-03clk: sunxi-ng: nkmp: Avoid GENMASK(-1, 0)Jernej Skrabec1-5/+13
2019-04-02clk: renesas: r8a77980: Fix RPC-IF module clock's parentSergei Shtylyov1-1/+1
2019-04-02clk: renesas: rcar-gen3: Rename DRIF clocksTakeshi Kihara4-34/+35
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of Audio-DMACTakeshi Kihara7-11/+11
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of SYS-DMACTakeshi Kihara4-8/+8
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of HS-USBKazuya Mizuguchi6-7/+7
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCIKazuya Mizuguchi6-12/+12
2019-04-02clk: renesas: r8a774c0: Add Z2 clockSimon Horman1-0/+1
2019-04-02clk: renesas: r8a77990: Add Z2 clockTakeshi Kihara1-0/+1
2019-04-02clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parentsSimon Horman1-2/+2
2019-04-02clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2Simon Horman5-5/+3