| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2021-01-05 | memory: tegra124-emc: Make driver modular | Dmitry Osipenko | 5 | -15/+75 |
| 2021-01-05 | clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS subsystems | Liu Ying | 1 | -0/+10 |
| 2021-01-05 | clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2() | Liu Ying | 1 | -2/+10 |
| 2021-01-05 | clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks | Liu Ying | 1 | -0/+2 |
| 2021-01-05 | clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks | Liu Ying | 1 | -0/+2 |
| 2021-01-04 | clk: meson: meson8b: remove compatibility code for old .dtbs | Martin Blumenstingl | 1 | -40/+5 |
| 2021-01-04 | clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate() | Martin Blumenstingl | 1 | -2/+3 |
| 2021-01-04 | clk: meson: clk-pll: make "ret" a signed integer | Martin Blumenstingl | 1 | -1/+2 |
| 2021-01-04 | clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLL | Martin Blumenstingl | 1 | -1/+1 |
| 2020-12-28 | clk: renesas: r8a779a0: Add RWDT clocks | Wolfram Sang | 1 | -0/+9 |
| 2020-12-28 | clk: renesas: r8a779a0: Add VSPX clock support | Kieran Bingham | 1 | -0/+4 |
| 2020-12-28 | clk: renesas: r8a779a0: Add VSPD clock support | Kieran Bingham | 1 | -0/+2 |
| 2020-12-28 | clk: renesas: r8a779a0: Add FCPVD clock support | Kieran Bingham | 1 | -0/+2 |
| 2020-12-28 | clk: renesas: r8a77995: Add TMU clocks | Niklas Söderlund | 1 | -0/+5 |
| 2020-12-28 | clk: renesas: r8a77990: Add TMU clocks | Niklas Söderlund | 1 | -0/+5 |
| 2020-12-28 | clk: renesas: r8a77965: Add TMU clocks | Niklas Söderlund | 1 | -0/+5 |
| 2020-12-28 | clk: renesas: r8a7796: Add TMU clocks | Niklas Söderlund | 1 | -0/+5 |
| 2020-12-21 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 99 | -1380/+8252 |
| 2020-12-20 | Merge branches 'clk-ingenic', 'clk-vc5', 'clk-cleanup', 'clk-canaan' and 'clk... | Stephen Boyd | 7 | -10/+19 |
| 2020-12-20 | Merge branches 'clk-ti', 'clk-analog', 'clk-trace', 'clk-at91' and 'clk-silab... | Stephen Boyd | 20 | -280/+905 |
| 2020-12-20 | Merge branches 'clk-tegra', 'clk-imx', 'clk-sifive', 'clk-mediatek' and 'clk-... | Stephen Boyd | 27 | -726/+1673 |
| 2020-12-20 | Merge branches 'clk-amlogic', 'clk-rockchip', 'clk-of', 'clk-freescale' and '... | Stephen Boyd | 23 | -47/+1199 |
| 2020-12-20 | Merge branches 'clk-doc', 'clk-qcom', 'clk-simplify', 'clk-hw', 'clk-renesas'... | Stephen Boyd | 25 | -317/+4456 |
| 2020-12-19 | clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts" | Geert Uytterhoeven | 1 | -2/+2 |
| 2020-12-19 | clk: ingenic: Fix divider calculation with div tables | Paul Cercueil | 1 | -4/+10 |
| 2020-12-19 | clk: sunxi-ng: Make sure divider tables have sentinel | Jernej Skrabec | 2 | -0/+2 |
| 2020-12-19 | clk: s2mps11: Fix a resource leak in error handling paths in the probe function | Christophe JAILLET | 1 | -0/+1 |
| 2020-12-19 | clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9 | Terry Zhou | 1 | -2/+2 |
| 2020-12-19 | clk: si5351: Wait for bit clear after PLL reset | Sascha Hauer | 1 | -3/+10 |
| 2020-12-19 | clk: at91: sam9x60: remove atmel,osc-bypass support | Alexandre Belloni | 1 | -5/+1 |
| 2020-12-19 | clk: at91: sama7g5: register cpu clock | Claudiu Beznea | 1 | -7/+6 |
| 2020-12-19 | clk: at91: clk-master: re-factor master clock | Claudiu Beznea | 14 | -146/+542 |
| 2020-12-19 | clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz | Claudiu Beznea | 1 | -14/+47 |
| 2020-12-19 | clk: at91: sama7g5: decrease lower limit for MCK0 rate | Claudiu Beznea | 1 | -1/+1 |
| 2020-12-19 | clk: at91: sama7g5: remove mck0 from parent list of other clocks | Claudiu Beznea | 1 | -29/+26 |
| 2020-12-19 | clk: at91: clk-sam9x60-pll: allow runtime changes for pll | Claudiu Beznea | 4 | -41/+197 |
| 2020-12-19 | clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics | Eugen Hristev | 1 | -2/+2 |
| 2020-12-19 | clk: at91: clk-master: add 5th divisor for mck master | Eugen Hristev | 2 | -2/+2 |
| 2020-12-19 | clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT | Eugen Hristev | 1 | -2/+4 |
| 2020-12-19 | dt-bindings: clock: at91: add sama7g5 pll defines | Eugen Hristev | 1 | -3/+3 |
| 2020-12-19 | clk: at91: sama7g5: fix compilation error | Claudiu Beznea | 1 | -2/+4 |
| 2020-12-19 | clk: bcm: dvp: Add MODULE_DEVICE_TABLE() | Nicolas Saenz Julienne | 1 | -0/+1 |
| 2020-12-19 | clk: bcm: dvp: drop a variable that is assigned to only | Uwe Kleine-König | 1 | -2/+1 |
| 2020-12-17 | clk: Trace clk_set_rate() "range" functions | Maxime Ripard | 1 | -0/+6 |
| 2020-12-17 | clk: axi-clkgen: move the OF table at the bottom of the file | Alexandru Ardelean | 1 | -9/+9 |
| 2020-12-17 | clk: axi-clkgen: wrap limits in a struct and keep copy on the state object | Alexandru Ardelean | 1 | -17/+31 |
| 2020-12-17 | clk: ti: omap5: Fix reboot DPLL lock failure when using ABE TIMERs | David Shah | 1 | -1/+11 |
| 2020-12-17 | clk: ti: Fix memleak in ti_fapll_synth_setup | Zhang Qilong | 1 | -2/+9 |
| 2020-12-17 | clk: Add hardware-enable column to clk summary | Dmitry Osipenko | 1 | -4/+11 |
| 2020-12-17 | clk: mediatek: Make mtk_clk_register_mux() a static function | Weiyi Lu | 2 | -5/+1 |