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2021-07-27clk: mediatek: Add MT8192 imp i2c wrapper clock supportChun-Jie Chen3-0/+126
2021-07-27clk: mediatek: Add MT8192 imgsys clock supportChun-Jie Chen3-0/+77
2021-07-27clk: mediatek: Add MT8192 camsys clock supportChun-Jie Chen3-0/+114
2021-07-27clk: mediatek: Add MT8192 audio clock supportChun-Jie Chen3-0/+125
2021-07-27clk: mediatek: Add MT8192 basic clocks supportChun-Jie Chen5-4/+1358
2021-07-27clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providersChun-Jie Chen2-0/+31
2021-07-27clk: mediatek: Add configurable enable control to mtk_pll_dataChun-Jie Chen2-14/+21
2021-07-27clk: mediatek: Fix asymmetrical PLL enable and disable controlChun-Jie Chen1-4/+16
2021-07-27clk: mediatek: Get regmap without syscon compatible checkChun-Jie Chen4-4/+4
2021-07-26clk: socfpga: agilex: add the bypass register for s2f_usr0 clockDinh Nguyen1-1/+1
2021-07-26clk: socfpga: agilex: fix up s2f_user0_clk representationDinh Nguyen1-0/+9
2021-07-26clk: socfpga: agilex: fix the parents of the psi_ref_clkDinh Nguyen1-4/+4
2021-07-26clk: hisilicon: hi3559a: select RESET_HISIRandy Dunlap1-0/+1
2021-07-26clk: stm32f4: fix post divisor setup for I2S/SAI PLLsDario Binacchi1-5/+5
2021-07-26clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2Lad Prabhakar1-1/+2
2021-07-20clk: qcom: Add video clock controller driver for SC7280Taniya Das3-0/+334
2021-07-20clk: qcom: Add graphics clock controller driver for SC7280Taniya Das3-0/+500
2021-07-20clk: qcom: Add display clock controller driver for SC7280Taniya Das3-0/+918
2021-07-19clk: renesas: r9a07g044: Add clock and reset entries for ADCLad Prabhakar1-0/+6
2021-07-19clk: renesas: r9a07g044: Add clock and reset entries for CANFDLad Prabhakar1-0/+4
2021-07-19clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]Geert Uytterhoeven4-3/+3
2021-07-19clk: renesas: r9a07g044: Add GPIO clock and reset entriesLad Prabhakar1-0/+5
2021-07-19clk: renesas: r9a07g044: Add SSIF-2 clock and reset entriesBiju Das1-0/+20
2021-07-19clk: renesas: r9a07g044: Add USB clocks/resetsBiju Das1-0/+12
2021-07-19clk: renesas: r9a07g044: Add DMAC clocks/resetsBiju Das1-0/+8
2021-07-19clk: renesas: r9a07g044: Add I2C clocks/resetsBiju Das1-0/+12
2021-07-19clk: renesas: r8a779a0: Add the DSI clocksKieran Bingham1-1/+3
2021-07-19clk: renesas: r8a779a0: Add the DU clockKieran Bingham1-0/+1
2021-07-19clk: renesas: rzg2: Rename i2c-dvfs to iic-pmicGeert Uytterhoeven4-4/+4
2021-07-19clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get()Lad Prabhakar1-1/+1
2021-07-19clk: renesas: rzg2l: Avoid mixing error pointers and NULLDan Carpenter1-1/+1
2021-07-19clk: renesas: rzg2l: Fix a double free on errorDan Carpenter1-7/+1
2021-07-19clk: renesas: rzg2l: Fix return value and unused assignmentYang Li1-4/+2
2021-07-19clk: renesas: rzg2l: Remove unneeded semicolonYang Li1-1/+1
2021-07-16clk: rockchip: Add support for hclk_sfc on rk3036Jon Lin1-1/+1
2021-07-16clk: rockchip: rk3036: fix up the sclk_sfc parent errorJon Lin1-1/+2
2021-07-12dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitionsBiju Das3-64/+93
2021-07-12clk: renesas: r9a07g044: Add P2 Clock supportBiju Das2-0/+5
2021-07-12clk: renesas: r9a07g044: Fix P1 ClockBiju Das1-3/+3
2021-07-12clk: renesas: r9a07g044: Rename divider tableBiju Das1-3/+4
2021-07-12clk: renesas: rzg2l: Add multi clock PM supportBiju Das1-22/+29
2021-07-08Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds6-54/+101
2021-07-02Merge branch 'akpm' (patches from Andrew)Linus Torvalds1-0/+4
2021-07-01Revert "clk: divider: Switch from .round_rate to .determine_rate by default"Stephen Boyd1-9/+9
2021-07-01Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds95-1191/+16314
2021-07-01kernel.h: split out panic and oops helpersAndy Shevchenko1-0/+4
2021-06-30clk: hisilicon: hi3559a: Drop __init markings everywhereStephen Boyd1-20/+19
2021-06-30clk: meson: regmap: switch to determine_rate for the dividersMartin Blumenstingl1-10/+9
2021-06-30clk: divider: Switch from .round_rate to .determine_rate by defaultMartin Blumenstingl1-9/+9
2021-06-30clk: divider: Add re-usable determine_rate implementationsMartin Blumenstingl1-14/+61