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2024-03-08clk: zynq: Prevent null pointer dereference caused by kmalloc failureDuoming Zhou1-5/+3
The kmalloc() in zynq_clk_setup() will return null if the physical memory has run out. As a result, if we use snprintf() to write data to the null address, the null pointer dereference bug will happen. This patch uses a stack variable to replace the kmalloc(). Fixes: 0ee52b157b8e ("clk: zynq: Add clock controller driver") Suggested-by: Michal Simek <[email protected]> Suggested-by: Stephen Boyd <[email protected]> Signed-off-by: Duoming Zhou <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Michal Simek <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2022-03-29clk: zynq: Update the parameters to zynq_clk_register_periph_clkShubhrajyoti Datta1-6/+6
In case there are only one gate or the two_gate is 0 the clk1 clock passed is not used. We are passing 0 which is arm_pll. Pass a invalid clock instead. Signed-off-by: Shubhrajyoti Datta <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-03-29clk: zynq: trivial warning fixShubhrajyoti Datta1-0/+1
Fix the below warning WARNING: Missing a blank line after declarations + int enable = !!(fclk_enable & BIT(i - fclk0)); + zynq_clk_register_fclk(i, clk_output_name[i], Signed-off-by: Shubhrajyoti Datta <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-12-02clk: zynq: pll: Fix kernel-doc warningsShubhrajyoti Datta1-6/+6
Fix the following kernel-doc warning drivers/clk/zynq/pll.c:15: warning: missing initial short description on line: * struct zynq_pll drivers/clk/zynq/pll.c:96: warning: No description found for return value of 'zynq_pll_is_enabled' drivers/clk/zynq/pll.c:116: warning: No description found for return value of 'zynq_pll_enable' drivers/clk/zynq/pll.c:187: warning: No description found for return value of 'clk_register_zynq_pll' Signed-off-by: Shubhrajyoti Datta <[email protected]> Link: https://lore.kernel.org/r/9929a56462bfdd491c43c233abc4341fc14dac1d.1637139796.git.shubhrajyoti.datta@xilinx.com Signed-off-by: Stephen Boyd <[email protected]>
2021-02-11clk: zynq: clkc: Remove various instances of an unused variable 'clk'Lee Jones1-38/+35
Fixes the following W=1 kernel build warning(s): drivers/clk/zynq/clkc.c: In function ‘zynq_clk_register_fclk’: drivers/clk/zynq/clkc.c:106:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable] drivers/clk/zynq/clkc.c: In function ‘zynq_clk_register_periph_clk’: drivers/clk/zynq/clkc.c:179:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable] drivers/clk/zynq/clkc.c: In function ‘zynq_clk_setup’: drivers/clk/zynq/clkc.c:220:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable] Cc: Michael Turquette <[email protected]> Cc: Stephen Boyd <[email protected]> Cc: Michal Simek <[email protected]> Cc: "Sören Brinkmann" <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Lee Jones <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-02-10clk: zynq: pll: Fix kernel-doc formatting in 'clk_register_zynq_pll's headerLee Jones1-6/+6
Fixes the following W=1 kernel build warning(s): drivers/clk/zynq/pll.c:187: warning: Function parameter or member 'name' not described in 'clk_register_zynq_pll' drivers/clk/zynq/pll.c:187: warning: Function parameter or member 'parent' not described in 'clk_register_zynq_pll' drivers/clk/zynq/pll.c:187: warning: Function parameter or member 'pll_ctrl' not described in 'clk_register_zynq_pll' drivers/clk/zynq/pll.c:187: warning: Function parameter or member 'pll_status' not described in 'clk_register_zynq_pll' drivers/clk/zynq/pll.c:187: warning: Function parameter or member 'lock_index' not described in 'clk_register_zynq_pll' drivers/clk/zynq/pll.c:187: warning: Function parameter or member 'lock' not described in 'clk_register_zynq_pll' Cc: Michael Turquette <[email protected]> Cc: Stephen Boyd <[email protected]> Cc: Michal Simek <[email protected]> Cc: "Sören Brinkmann" <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Lee Jones <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Michal Simek <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 401Thomas Gleixner2-25/+2
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license v2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 2 file(s). Signed-off-by: Thomas Gleixner <[email protected]> Reviewed-by: Allison Randal <[email protected]> Cc: [email protected] Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner1-0/+1
Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-04-23clk: core: replace clk_{readl,writel} with {readl,writel}Jonas Gorski2-12/+12
Now that clk_{readl,writel} is just an alias for {readl,writel}, we can switch all users of clk_* to use the accessors directly and remove the helpers. Signed-off-by: Jonas Gorski <[email protected]> [[email protected]: Also convert renesas file so that this can be compile independently] Signed-off-by: Stephen Boyd <[email protected]>
2018-08-30clk: Convert to using %pOFn instead of device_node.nameRob Herring1-2/+2
In preparation to remove the node name pointer from struct device_node, convert printf users to use the %pOFn format specifier. Cc: Eugeniy Paltsev <[email protected]> Cc: Michael Turquette <[email protected]> Cc: Stephen Boyd <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2016-03-02clk: zynq: Remove CLK_IS_ROOTStephen Boyd1-2/+1
This flag is a no-op now. Remove usage of the flag. Reviewed-by: Sören Brinkmann <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-09-01Merge tag 'armsoc-soc' of ↵Linus Torvalds1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Olof Johansson: "New or improved SoC support: - add support for Atmel's SAMA5D2 SoC - add support for Freescale i.MX6UL - improved support for TI's DM814x platform - misc fixes and improvements for RockChip platforms - Marvell MVEBU suspend/resume support A few driver changes that ideally would belong in the drivers branch are also here (acked by appropriate maintainers): - power key input driver for Freescale platforms (svns) - RTC driver updates for Freescale platforms (svns/mxc) - clk fixes for TI DM814/816X + a bunch of other changes for various platforms" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits) ARM: rockchip: pm: Fix PTR_ERR() argument ARM: imx: mach-imx6ul: Fix allmodconfig build clk: ti: fix for definition movement ARM: uniphier: drop v7_invalidate_l1 call at secondary entry memory: kill off set_irq_flags usage rtc: snvs: select option REGMAP_MMIO ARM: brcmstb: select ARCH_DMA_ADDR_T_64BIT for LPAE ARM: BCM: Enable ARM erratum 798181 for BRCMSTB ARM: OMAP2+: Fix power domain operations regression caused by 81xx ARM: rockchip: enable PMU_GPIOINT_WAKEUP_EN when entering shallow suspend ARM: rockchip: set correct stabilization thresholds in suspend ARM: rockchip: rename osc_switch_to_32k variable ARM: imx6ul: add fec MAC refrence clock and phy fixup init ARM: imx6ul: add fec bits to GPR syscon definition rtc: mxc: add support of device tree dt-binding: document the binding for mxc rtc rtc: mxc: use a second rtc clock ARM: davinci: cp_intc: use IRQCHIP_SKIP_SET_WAKE instead of irq_set_wake callback soc: mediatek: Fix SCPSYS compilation ARM: at91/soc: add basic support for new sama5d2 SoC ...
2015-07-31clk: zynq: remove redundant $(CONFIG_ARCH_ZYNQ) in MakefileMasahiro Yamada1-1/+1
Kbuild descends into drivers/clk/zynq/ only when CONFIG_ARCH_ZYNQ is enabled. (see drivers/clk/Makefile) $(CONFIG_ARCH_ZYNQ) in drivers/clk/zynq/Makefile always evaluates to 'y'. Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2015-07-20clk: zynq: Include clk.hStephen Boyd1-0/+1
This clock provider uses the consumer API, so include clk.h explicitly. Acked-by: Sören Brinkmann <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-06-04clk: make several parent names constUwe Kleine-König1-9/+16
Since commit 2893c379461a ("clk: make strings in parent name arrays const") the name of parent clocks can be const. So add more const in several clock drivers. Signed-off-by: Uwe Kleine-König <[email protected]> Acked-by: Heiko Stuebner <[email protected]> Acked-by: Sylwester Nawrocki <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-04-12clk: don't use __initconst for non-const arraysUwe Kleine-König1-12/+12
The statement static const char *name[]; defines a modifiable array of pointers to constant chars. That is *name[0] = 'f'; is forbidden, but name[0] = "f"; is not. So marking an array that is defined as above with __initconst is wrong. Either an additional const must be added such that the whole definition reads: static const char *const name[] __initconst; or where this is not possible __initdata must be used. Signed-off-by: Uwe Kleine-König <[email protected]> Signed-off-by: Michael Turquette <[email protected]>
2015-01-27clk: zynq: Force CPU_2X clock to be ungatedSoren Brinkmann1-0/+1
The CPU_2X clock does not have a classical in-kernel user, but is, amongst other things, required for OCM and debug access. Make sure this clock is not mistakenly disabled during boot up by enabling it in the platform's clock driver. Cc: [email protected] # 3.11+ Fixes: 0ee52b157b8e 'clk: zynq: Add clock controller driver' Signed-off-by: Soren Brinkmann <[email protected]> Signed-off-by: Michael Turquette <[email protected]>
2014-09-09clk: zynq: Move const initdata into correct code sectionSoren Brinkmann1-15/+14
Use __initconst instead of __initdata for constant init data. Signed-off-by: Soren Brinkmann <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-09-09clk: zynq: Remove pointless return at end of void functionSoren Brinkmann1-1/+0
Signed-off-by: Soren Brinkmann <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-09-09clk: zynq: Remove unnecessary OOM messageSoren Brinkmann1-3/+1
As checkpatch suggests: WARNING: Possible unnecessary 'out of memory' message, remove an error message after failing kmalloc() from the PLL driver. Signed-off-by: Soren Brinkmann <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-04-22clk: zynq: Leave debug clocks in bootup stateSoren Brinkmann1-0/+12
Make sure debug clocks stay enabled if the bootloader enabled them. Otherwise debug HW may crash due to bus-hangs caused by stopped clocks. Signed-off-by: Soren Brinkmann <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2014-04-05Merge tag 'clk-for-linus-3.15' of ↵Linus Torvalds2-11/+11
git://git.linaro.org/people/mike.turquette/linux Pull clock framework changes from Mike Turquette: "The clock framework changes for 3.15 look similar to past pull requests. Mostly clock driver updates, more Device Tree support in the form of common functions useful across platforms and a handful of features and fixes to the framework core" * tag 'clk-for-linus-3.15' of git://git.linaro.org/people/mike.turquette/linux: (86 commits) clk: shmobile: fix setting paretn clock rate clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1 clk: Fix minor errors in of_clk_init() function comments clk: reverse default clk provider initialization order in of_clk_init() clk: sirf: update copyright years to 2014 clk: mmp: try to use closer one when do round rate clk: mmp: fix the wrong calculation formula clk: mmp: fix wrong mask when calculate denominator clk: st: Adds quadfs clock binding clk: st: Adds clockgen-vcc and clockgen-mux clock binding clk: st: Adds clockgen clock binding clk: st: Adds divmux and prediv clock binding clk: st: Support for A9 MUX clocks clk: st: Support for ClockGenA9/DDR/GPU clk: st: Support for QUADFS inside ClockGenB/C/D/E/F clk: st: Support for VCC-mux and MUX clocks clk: st: Support for PLLs inside ClockGenA(s) clk: st: Support for DIVMUX and PreDiv Clocks clk: support hardware-specific debugfs entries clk: s2mps11: Use of_get_child_by_name ...
2014-03-17ARM: zynq: Move of_clk_init from clock driverMichal Simek1-2/+0
Move of_clk_init() from clock driver to enable options not to use zynq clock driver. Use for example fixed clock setting. Signed-off-by: Michal Simek <[email protected]>
2014-02-25clk: zynq: Use clk_readl/clk_writel helper functionMichal Simek2-11/+11
Do not use readl/writel directly because the whole clk subsystem is using clk_readl/clk_writel functions. Signed-off-by: Michal Simek <[email protected]> Acked-by: Soren Brinkmann <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-02-10ARM: zynq: Map I/O memory on clkc initMichal Simek1-26/+63
The clkc has its registers in the range of the slcr. Instead of passing around the slcr base address pointer, let the clkc get the address from the DT. This prepares the slcr to be a real driver with multiple memory ranges (slcr, clocks, pinctrl,...) Signed-off-by: Steffen Trumtrar <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2013-12-20clk/zynq/clkc: Add 'fclk-enable' featureSoren Brinkmann1-3/+15
In some use cases Zynq's FPGA clocks are used as static clock generators for IP in the FPGA part of the SOC for which no Linux driver exists and would control those clocks. To avoid automatic gating of these clocks in such cases a new property - fclk-enable - is added to the clock controller's DT description to accomodate such use cases. It's value is a bitmask, where a set bit results in enabling the corresponding FCLK through the clkc. FPGA clocks are handled following the rules below: If an FCLK is not enabled by bootloaders, that FCLK will be disabled in Linux. Drivers can enable and control it through the CCF as usual. If an FCLK is enabled by bootloaders AND the corresponding bit in the 'fclk-enable' DT property is set, that FCLK will be enabled by the clkc, resulting in an off by one reference count for that clock. Ensuring it will always be running. Signed-off-by: Soren Brinkmann <[email protected]> Acked-by: Michal Simek <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2013-10-07clk/zynq: Fix possible memory leakFelipe Pena1-1/+15
The zynq_clk_register_fclk function can leak memory (fclk_lock) when unable to alloc memory for fclk_gate_lock Signed-off-by: Felipe Pena <[email protected]> Acked-by: Sören Brinkmann <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2013-09-09Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linuxLinus Torvalds2-39/+62
Pull clock framework changes from Michael Turquette: "The common clk framework changes for 3.12 are dominated by clock driver patches, both new drivers and fixes to existing. A high percentage of these are for Samsung platforms like Exynos. Core framework fixes and some new features like automagical clock re-parenting round out the patches" * tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits) clk: only call get_parent if there is one clk: samsung: exynos5250: Simplify registration of PLL rate tables clk: samsung: exynos4: Register PLL rate tables for Exynos4x12 clk: samsung: exynos4: Register PLL rate tables for Exynos4210 clk: samsung: exynos4: Reorder registration of mout_vpllsrc clk: samsung: pll: Add support for rate configuration of PLL46xx clk: samsung: pll: Use new registration method for PLL46xx clk: samsung: pll: Add support for rate configuration of PLL45xx clk: samsung: pll: Use new registration method for PLL45xx clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls clk: samsung: exynos4: Remove checks for DT node clk: samsung: exynos4: Remove unused static clkdev aliases clk: samsung: Modify _get_rate() helper to use __clk_lookup() clk: samsung: exynos4: Use separate aliases for cpufreq related clocks clocksource: samsung_pwm_timer: Get clock from device tree ARM: dts: exynos4: Specify PWM clocks in PWM node pwm: samsung: Update DT bindings documentation to cover clocks clk: Move symbol export to proper location clk: fix new_parent dereference before null check clk: wm831x: Initialise wm831x pointer on init ...
2013-08-20Merge tag 'zynq-clk-for-3.12' of git://git.xilinx.com/linux-xlnx into clk-nextMike Turquette1-5/+14
arm: Xilinx Zynq clock changes for v3.12 Just small two changes where the first fixes documentation and the second improves code readability.
2013-08-20clk/zynq/pll: Use #defines for fbdiv min/max valuesSoren Brinkmann1-4/+7
Use more descriptive #defines for the minimum and maximum PLL feedback divider. Signed-off-by: Soren Brinkmann <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2013-08-20clk/zynq/pll: Fix documentation for PLL register functionSoren Brinkmann1-1/+7
Signed-off-by: Soren Brinkmann <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2013-08-19clk: add CLK_SET_RATE_NO_REPARENT flagJames Hogan1-36/+50
Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes being reparented during clk_set_rate. To avoid breaking existing platforms, all callers of clk_register_mux() are adjusted to pass the new flag. Platform maintainers are encouraged to remove the flag if they wish to allow mux reparenting on set_rate. Signed-off-by: James Hogan <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Cc: Mike Turquette <[email protected]> Cc: Russell King <[email protected]> Cc: Sascha Hauer <[email protected]> Cc: Stephen Warren <[email protected]> Cc: Viresh Kumar <[email protected]> Cc: Kukjin Kim <[email protected]> Cc: Haojian Zhuang <[email protected]> Cc: Chao Xie <[email protected]> Cc: Arnd Bergmann <[email protected]> Cc: "Emilio López" <[email protected]> Cc: Gregory CLEMENT <[email protected]> Cc: Maxime Ripard <[email protected]> Cc: Prashant Gaikwad <[email protected]> Cc: Thierry Reding <[email protected]> Cc: Peter De Schrijver <[email protected]> Cc: Pawel Moll <[email protected]> Cc: Catalin Marinas <[email protected]> Cc: Andrew Chew <[email protected]> Cc: Doug Anderson <[email protected]> Cc: Heiko Stuebner <[email protected]> Cc: Paul Walmsley <[email protected]> Cc: Sylwester Nawrocki <[email protected]> Cc: Thomas Abraham <[email protected]> Cc: Tomasz Figa <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Tested-by: Haojian Zhuang <[email protected]> Acked-by: Stephen Warren <[email protected]> [tegra] Acked-by: Maxime Ripard <[email protected]> [sunxi] Acked-by: Sören Brinkmann <[email protected]> [Zynq] Signed-off-by: Mike Turquette <[email protected]>
2013-08-13clk/zynq/clkc: Add CLK_SET_RATE_PARENT flag to ethernet muxesSoren Brinkmann1-4/+6
Zynq's Ethernet clocks are created by the following hierarchy: mux0 ---> div0 ---> div1 ---> mux1 ---> gate Rate change requests on the gate have to propagate all the way up to div0 to properly leverage all dividers. Mux1 was missing the CLK_SET_RATE_PARENT flag, which is required to achieve this. This does not fix a specific regression but the clock driver was merged for 3.11-rc1, so best to fix the known bugs before the release. Signed-off-by: Soren Brinkmann <[email protected]> Signed-off-by: Michal Simek <[email protected]> Signed-off-by: Mike Turquette <[email protected]> [[email protected]: added to changelog]
2013-08-13clk/zynq/clkc: Add dedicated spinlock for the SWDTSoren Brinkmann1-1/+2
The clk_mux for the system watchdog timer reused the register lock dedicated to the Ethernet module - for no apparent reason. Add a lock dedicated to the SWDT's clock register to remove this wrong dependency. This does not fix a specific regression but the clock driver was merged for 3.11-rc1, so best to fix the known bugs before the release. Signed-off-by: Soren Brinkmann <[email protected]> Signed-off-by: Michal Simek <[email protected]> Signed-off-by: Mike Turquette <[email protected]> [[email protected]: added to changelog]
2013-05-27arm: zynq: Migrate platform to clock controllerSoren Brinkmann1-0/+3
Migrate the Zynq platform and its drivers to use the new clock controller driver. Signed-off-by: Soren Brinkmann <[email protected]> Cc: John Stultz <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Greg Kroah-Hartman <[email protected]> Cc: Jiri Slaby <[email protected]> Cc: [email protected] Signed-off-by: Michal Simek <[email protected]> Acked-by: Mike Turquette <[email protected]>
2013-05-27clk: zynq: Add clock controller driverSoren Brinkmann1-0/+533
Add a clock controller driver and documentation. Signed-off-by: Soren Brinkmann <[email protected]> Cc: Grant Likely <[email protected]> Cc: Rob Herring <[email protected]> Cc: Rob Landley <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Michal Simek <[email protected]> Acked-by: Mike Turquette <[email protected]>
2013-05-21clk: zynq: Factor out PLL driverSoren Brinkmann1-0/+235
Refactor the PLL driver so it works with the clock controller driver. Signed-off-by: Soren Brinkmann <[email protected]> Signed-off-by: Michal Simek <[email protected]> Acked-by: Mike Turquette <[email protected]>
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