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The def_bool y PMC_ATOM Kconfig option provides a couple of symbols used
by the code enabled by the X86_INTEL_LPSS option and it registers some
clocks. These clocks are only registered on Bay Trail, Cherry Trail and
Brasswell Intel SoCs and kernels targeting these SoCs must always have
the X86_INTEL_LPSS option enabled otherwise many things will not work.
Building the PMC_ATOM code on kernels which are not targeting the
mentioned SoCs and which do not have the X86_INTEL_LPSS enabled is
not useful.
This means that we can simplify things by replacing the PMC_ATOM Kconfig
option in Makefiles with X86_INTEL_LPSS and then drop the option.
Cc: Paul Gortmaker <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Andy Shevchenko <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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The LPT stands for Lynxpoint PCH. However the driver is used on a few
Intel Atom SoCs. Rename it to reflect this in a way how another clock
driver, i.e. clk-pmc-atom, is called.
Signed-off-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Rafael J. Wysocki <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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AMD SoC general pupose clk is present in new platforms with
minor differences. We can reuse the same clk driver for other
platforms. Hence, changing name from ST(SoC) to FCH(IP)
Signed-off-by: Akshu Agrawal <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>
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Clock Generation Unit(CGU) is a new clock controller IP of a forthcoming
Intel network processor SoC named Lightning Mountain(LGM). It provides
programming interfaces to control & configure all CPU & peripheral clocks.
Add common clock framework based clock controller driver for CGU.
Signed-off-by: Rahul Tanwar <[email protected]>
Link: https://lkml.kernel.org/r/42a4f71847714df482bacffdcd84341a4052800b.1587102634.git.rahul.tanwar@linux.intel.com
[[email protected]: Kill init function to alloc and cleanup newline]
Signed-off-by: Stephen Boyd <[email protected]>
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Add SPDX license identifiers to all Make/Kconfig files which:
- Have no license information of any form
These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:
GPL-2.0-only
Signed-off-by: Thomas Gleixner <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Stoney SoC provides oscout clock. This clock can support 25Mhz and
48Mhz of frequency.
The clock is available for general system use.
Signed-off-by: Akshu Agrawal <[email protected]>
Reviewed-by: Daniel Kurtz <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>
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The BayTrail and CherryTrail platforms provide platform clocks
through their Power Management Controller (PMC).
The SoC supports up to 6 clocks (PMC_PLT_CLK[0..5]) with a
frequency of either 19.2 MHz (PLL) or 25 MHz (XTAL) for BayTrail
and a frequency of 19.2 MHz (XTAL) for CherryTrail. These clocks
are available for general system use, where appropriate, and each
have Control & Frequency register fields associated with them.
Port from legacy by Pierre Bossart, integration in clock framework
by Irina Tirdea
Signed-off-by: Irina Tirdea <[email protected]>
Signed-off-by: Pierre-Louis Bossart <[email protected]>
Acked-by: Andy Shevchenko <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Devices on the Intel Lynxpoint Low Power Subsystem (LPSS) have some
common features that aren't shared with any other platform devices,
including the clock and LTR (Latency Tolerance Reporting) registers.
It is better to handle those features in common code than to bother
device drivers with doing that (I/O functionality-wise the LPSS
devices are generally compatible with other devices that don't
have those special registers and may be handled by the same drivers).
The clock registers of the LPSS devices are now taken care of by
the special clk-x86-lpss driver, but the MMIO mappings used for
accessing those registers can also be used for accessing the LTR
registers on those devices (LTR support for the Lynxpoint LPSS is
going to be added by a subsequent patch). Thus it is convenient
to add a special ACPI scan handler for the Lynxpoint LPSS devices
that will create the MMIO mappings for accessing the clock (and
LTR in the future) registers and will register the LPSS devices'
clocks, so the clk-x86-lpss driver will only need to take care of
the main Lynxpoint LPSS clock.
Introduce a special ACPI scan handler for Intel Lynxpoint LPSS
devices as described above. This also reduces overhead related to
browsing the ACPI namespace in search of the LPSS devices before the
registration of their clocks, removes some LPSS-specific (and
somewhat ugly) code from acpi_platform.c and shrinks the overall code
size slightly.
Signed-off-by: Mika Westerberg <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>
Acked-by: Mike Turquette <[email protected]>
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Intel Lynxpoint Low Power Subsystem hosts peripherals like UART, I2C and
SPI controllers. For most of these there is a configuration register that
allows software to enable and disable the functional clock. Disabling the
clock while the peripheral is not used saves power.
In order to take advantage of this we add a new clock gate of type
lpss_gate that just re-uses the ordinary clk_gate but in addition is able
to enumerate the base address register of the device using ACPI.
We then create a clock tree that models the Lynxpoint LPSS clocks using
these gates and fixed clocks so that we can pass clock rate to the drivers
as well.
Signed-off-by: Heikki Krogerus <[email protected]>
Signed-off-by: Mika Westerberg <[email protected]>
Reviewed-by: Mark Brown <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>
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