| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2021-06-27 | clk: agilex/stratix10: add support for the 2nd bypass | Dinh Nguyen | 1 | -0/+2 |
| 2021-03-30 | clk: socfpga: Convert to s10/agilex/n5x to use clk_hw | Dinh Nguyen | 1 | -12/+12 |
| 2021-02-12 | clk: socfpga: agilex: add clock driver for eASIC N5X platform | Dinh Nguyen | 1 | -1/+16 |
| 2020-05-26 | clk: socfpga: agilex: add clock driver for the Agilex platform | Dinh Nguyen | 1 | -0/+2 |
| 2020-05-26 | clk: socfpga: stratix10: use new parent data scheme | Dinh Nguyen | 1 | -4/+4 |
| 2020-02-12 | clk: socfpga: stratix10: simplify parameter passing | Dinh Nguyen | 1 | -17/+8 |
| 2018-04-06 | clk: socfpga: stratix10: add clock driver for Stratix10 platform | Dinh Nguyen | 1 | -0/+80 |