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2024-09-21clk: Switch back to struct platform_driver::remove()Uwe Kleine-König1-1/+1
After commit 0edb555a65d1 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all clk drivers to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. Signed-off-by: Uwe Kleine-König <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Geert Uytterhoeven <[email protected]> # renesas Signed-off-by: Stephen Boyd <[email protected]>
2024-09-21Merge branches 'clk-assigned-rates', 'clk-renesas' and 'clk-scmi' into clk-nextStephen Boyd14-187/+1526
* clk-assigned-rates: clk: clk-conf: support assigned-clock-rates-u64 * clk-renesas: (34 commits) clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT clk: renesas: rzv2h: Add support for dynamic switching divider clocks clk: renesas: r9a08g045: Add clocks, resets and power domains for USB dt-bindings: clock: renesas,cpg-clocks: Add top-level constraints clk: renesas: r8a779h0: Add CANFD clock clk: renesas: Add RZ/V2H(P) CPG driver clk: renesas: Add family-specific clock driver for RZ/V2H(P) dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG clk: renesas: r8a779h0: Add PWM clock dt-bindings: clock: renesas,cpg-mssr: Document RZ/G2M v3.0 (r8a774a3) clock clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs clk: renesas: rcar-gen4: Remove unused fixed PLL clock types clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLs clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLs clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLs clk: renesas: r8a779a0: Use defines for PLL control registers clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLs clk: renesas: rcar-gen4: Add support for fixed variable PLLs clk: renesas: rcar-gen4: Add support for variable fractional PLLs ... * clk-scmi: clk: scmi: add is_prepared hook
2024-09-02clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDTLad Prabhakar2-0/+88
Add clock and reset entries for Generic Timer (GTM), I2C Bus Interface (RIIC), SD/MMC Host Interface (SDHI) and Watchdog Timer (WDT) IP blocks. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-09-02clk: renesas: rzv2h: Add support for dynamic switching divider clocksLad Prabhakar2-3/+201
Add support for dynamic switching divider clocks. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-09-02clk: renesas: r9a08g045: Add clocks, resets and power domains for USBClaudiu Beznea1-0/+17
Add clocks, resets and power domains for USB modules available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-08-20clk: renesas: r8a779h0: Add CANFD clockCong Dang1-0/+1
Add the CANFD module clock on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/9bf71bfda338ee5411751174b03b9e870cc818e3.1722519424.git.geert+renesas@glider.be
2024-08-20clk: renesas: Add RZ/V2H(P) CPG driverLad Prabhakar5-0/+94
Add RZ/V2H(P) CPG driver. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-08-02clk: Use of_property_present()Rob Herring (Arm)1-1/+1
Use of_property_present() to test for property presence rather than of_(find|get)_property(). This is part of a larger effort to remove callers of of_find_property() and similar functions. of_(find|get)_property() leak the DT struct property and data pointers which is a problem for dynamically allocated nodes which may be freed. Signed-off-by: Rob Herring (Arm) <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Linus Walleij <[email protected]> Acked-by: Geert Uytterhoeven <[email protected]> # clk-mstp.c Reviewed-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2024-08-02clk: renesas: Add family-specific clock driver for RZ/V2H(P)Lad Prabhakar4-0/+838
Add family-specific clock driver for RZ/V2H(P) SoCs. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-08-02clk: renesas: r8a779h0: Add PWM clockCong Dang1-0/+1
Add the module clock used by the PWM timers on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <[email protected]> [wsa: rebased] Signed-off-by: Wolfram Sang <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-07-30clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configsGeert Uytterhoeven5-28/+20
The default PLL2/3/4/6 multiplier and divider configurations are no longer used after the conversion to fixed or variable fractional PLL clock types. Note that the default configurations are still documented in the comments above the individual rcar_gen4_cpg_pll_config instances. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/d13526a86066992d6afdf9bee7c1a18da72f914f.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: rcar-gen4: Remove unused fixed PLL clock typesGeert Uytterhoeven2-24/+0
All users of the fixed default PLL2/3/4/6 clock types have been converted to fixed or variable fractional PLL clock types. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/c0229eb3518444f61173c6fb83bdcedb058dd079.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: rcar-gen4: Remove unused variable PLL2 clock typeGeert Uytterhoeven2-10/+0
The variable PLL2 clock type was superseded by the more generic variable fractional 8.25 PLL clock type, and its sole user was converted. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/8e5564958002351f29435f63de1304fb3b51a725.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLsGeert Uytterhoeven1-5/+5
Currently, all PLLs are modelled as fixed divider clocks, based on the state of the mode pins. However, the boot loader stack may have changed the actual PLL configuration from the default, leading to incorrect clock frequencies. Describe PLL1 as a fixed fractional PLL instead, and PLL2, PLL3, PLL4, and PLL6 as variable fractional PLLs. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/3beac7c44534ed153ce7cea5c31f4b0bb7b16ab0.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLsGeert Uytterhoeven1-7/+7
Currently, all PLLs but PLL2 are modelled as fixed divider clocks, based on the state of the mode pins. However, the boot loader stack may have changed the actual PLL configuration from the default, leading to incorrect clock frequencies. Describe PLL1 as a fixed fractional PLL instead, and PLL2, PLL3, PLL4, and PLL6 as variable fractional PLLs. Reformat nearby lines to retain a consistent layout. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/b98523ed08de7386944c5ae860eae107dc28be3e.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLsGeert Uytterhoeven1-6/+6
Currently, all PLLs are modelled as fixed divider clocks, based on the state of the mode pins. However, the boot loader stack may have changed the actual PLL configuration from the default, leading to incorrect clock frequencies. Describe PLL1 as a fixed fractional PLL instead, and PLL2, PLL3, and PLL6 as variable fractional PLLs. Note that the R-Car Gen4 clock driver does not support variable 9.24 PLLs yet, so the driver will downgrade them to fixed fractional PLLs, too. Reformat nearby lines to retain a consistent layout. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/8544571f507e00ed6fc61617d27c9e19de5e9d11.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: r8a779a0: Use defines for PLL control registersGeert Uytterhoeven1-4/+9
Add symbolic definitions for the various PLL control registers. Replace hardcoded register offsets by the new definitions. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/8cac464c7dfb15ecd299b8ab4ba88a16135f8123.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLsGeert Uytterhoeven2-0/+44
The custom clock driver that models the PLL clocks on R-Car Gen4 supports only fractional 8.25 PLLs, as used on R-Car V4H/V4M. R-Car S4-8 uses integer and fractional multiplication fields that are one bit larger resp. smaller, and a slightly different formula. Extend the existing support to fractional 9.24 PLL, and introduce new clock types and helper macros to describe these PLLs. Note that there is no use case for variable fractional 9.24 PLLs yet, as the Cortex-A55 cores on R-Car S4-8 do not support High Performance mode. Hence the PLL is always modeled as a fixed PLL, regardless of the description, Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/5684eda1260435c8eceabc274e0b18cb280a6341.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: rcar-gen4: Add support for fixed variable PLLsGeert Uytterhoeven2-10/+26
The custom clock driver that models PLL clocks on R-Car Gen4 supports variable clocks, while PLL1 uses a similar control register layout, but is read-only. Extend the existing support to fixed clocks and PLL1, and introduce a new clock type and helper macro to describe a fixed PLL. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/841fbb63d472c357b3ce291a5991db3b847f96d8.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: rcar-gen4: Add support for variable fractional PLLsGeert Uytterhoeven2-7/+18
The custom clock driver that models PLL clocks on R-Car Gen4 supports PLL2 on R-Car V4H/V4M only, while PLL3, PLL4, and PLL6 use the same control register layout. Extend the existing support to PLL3, PLL4, and PLL6, and introduce a new clock type and helper macro to describe these PLLs. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/84ead759782560ec5643711e6bdd787a751053ce.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: rcar-gen4: Add support for fractional multiplicationGeert Uytterhoeven1-16/+55
R-Car Gen4 PLLs support fractional multiplication, which can improve accuracy when configuring a specific frequency. Add support for fractional multiplication to the custom clock driver for PLLs, which is currently used only for PLL2 on R-Car V4H. While at it, add the missing blank line after the function. Note that Fractional Multiplication is not enabled by the driver, but used only if the boot loaded enabled it before. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/1a58ebef6f54460f49fb81ba9bbf288164de2646.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: rcar-gen4: Use defines for common CPG registersGeert Uytterhoeven5-21/+27
Add symbolic definitions for common CPG registers. Replace hardcoded register offsets by the new definitions. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/8ae48a5dac59cb5723fbca3842b93a9e51ffe1ca.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: rcar-gen4: Use FIELD_GET()Geert Uytterhoeven2-5/+11
Improve readability by using the FIELD_GET() helper instead of open-coding the same operation, and by adding field definitions to get rid of hardcoded values. While at it, move register definitions that are only used inside the rcar-gen4-cpg.c source file out of the rcar-gen4-cpg.h header file. Add a "CPG_" prefix to SD0CKCR1. Add comments where appropriate. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/fb19ad829738f02effa340fa04c178a162d41202.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: rcar-gen4: Clarify custom PLL clock supportGeert Uytterhoeven1-15/+17
The custom clock driver that models the PLL clocks on R-Car Gen4 assumes the integer and fractional[*] multiplication field sizes as used on R-Car V4H and V4M, representing a fractional 8.25 number. Rename the related definitions, functions, and structures to clarify this, and to prepare for the advent of support for the different field sizes on R-Car S4-8. [*] The fractional part is not yet supported. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/2ce9f9c75bfb6312129d416672f9691bbd11c0e7.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: rcar-gen4: Removed unused SSMODE_* definitionsGeert Uytterhoeven1-4/+0
All SSMODE operations are done using CPG_PLLxCR0_SSMODE*. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/19f84bfec94eab5f301a9c33563c285ab59b9b2a.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: rzg2l-cpg: Refactor to use priv for clks and base in clock ↵Lad Prabhakar1-28/+17
register functions Simplify the `rzg2l-cpg` driver by removing explicit passing of `clks` and `base` parameters in various clock registration functions. These values are now accessed directly from the `priv` structure. While at it, drop masking of parent clocks with 0xffff as nothing is ever stored in the high bits. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-07-30clk: renesas: rzg2l-cpg: Use devres API to register clocksLad Prabhakar1-6/+20
We are using devres APIs for divider, mux and pll5 clocks so for consistency use the devres APIs for module, fixed factor and PLL clocks. While at it switched to clk_hw_register() instead of clk_register() as this has been marked as deprecated interface. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-07-30clk: renesas: r8a779h0: Initial clock descriptions should be __initconstGeert Uytterhoeven1-3/+3
r8a779h0_core_clks[], r8a779h0_mod_clks[], and cpg_pll_configs[] are only used during initialization. Hence make them __initconst, so they will be freed later. Fixes: f077cab34df3010d ("clk: renesas: cpg-mssr: Add support for R-Car V4M") Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Niklas Söderlund <[email protected]> Link: https://lore.kernel.org/35bbcfb914ddb377fa77e3425e4e7e232c7c2cf9.1720794214.git.geert+renesas@glider.be
2024-07-30clk: renesas: r8a779g0: cpg_pll_configs should be __initconstGeert Uytterhoeven1-1/+1
cpg_pll_configs[] is only used during initialization. Hence make it __initconst, so it will be freed later. Fixes: 0ab55cf1834177a2 ("clk: renesas: cpg-mssr: Add support for R-Car V4H") Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Niklas Söderlund <[email protected]> Link: https://lore.kernel.org/ea806a096d47382f4f560b20f1038f03b4e44e0e.1720794214.git.geert+renesas@glider.be
2024-07-30clk: renesas: r8a779f0: cpg_pll_configs should be __initconstGeert Uytterhoeven1-1/+1
cpg_pll_configs[] is only used during initialization. Hence make it __initconst, so it will be freed later. Fixes: 24aaff6a6ce4c4de ("clk: renesas: cpg-mssr: Add support for R-Car S4-8") Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Niklas Söderlund <[email protected]> Link: https://lore.kernel.org/2261fc8291099445e1b319812dfd4f79c90296d2.1720794214.git.geert+renesas@glider.be
2024-07-30clk: renesas: r8a779a0: cpg_pll_configs should be __initconstGeert Uytterhoeven1-1/+1
cpg_pll_configs[] is only used during initialization. Hence make it __initconst, so it will be freed later. Fixes: 17bcc8035d2d19fc ("clk: renesas: cpg-mssr: Add support for R-Car V3U") Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Niklas Söderlund <[email protected]> Link: https://lore.kernel.org/a9819625329b188c298481402e1c55ac46093518.1720794214.git.geert+renesas@glider.be
2024-07-30clk: renesas: r9a08g045: Add DMA clocks and resetsClaudiu Beznea1-0/+3
Add the missing DMA clock and resets. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-07-30clk: renesas: r9a07g043: Add LCDC clock and reset entriesBiju Das1-0/+12
Add LCDC clock and reset entries to CPG driver. Signed-off-by: Biju Das <[email protected]> Acked-by: Conor Dooley <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-07-30clk: renesas: r8a779h0: Add PCIe clockYoshihiro Shimoda1-0/+1
Add the PCIe module clock, which is used by the PCIe module on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Yoshihiro Shimoda <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-06-27clk: renesas: r9a08g045: Add clock, reset and power domain support for I2CClaudiu Beznea1-0/+20
Add clock, reset and power domain support for the I2C channels available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-06-27clk: renesas: r8a779h0: Add Audio clocksKuninori Morimoto1-0/+2
Add module clocks for the Audio (SSI/SSIU) blocks on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Kuninori Morimoto <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-06-27clk: renesas: r9a08g045: Add clock, reset and power domain support for the ↵Claudiu Beznea1-0/+6
VBATTB IP The Renesas RZ/G3S SoC has an IP named Battery Backup Function (VBATTB) that generates the RTC clock. Add clock, reset and power domain support for it. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-06-24clk: renesas: Drop "Renesas" from individual driver descriptionsGeert Uytterhoeven1-2/+2
All configuration options are under the big "Renesas SoC clock support" umbrella, so there is no reason to repeat this for each driver. Hence drop "Renesas" from the few that do. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/185323de4d38b9b599775c1b64ce4171551b98d5.1718177124.git.geert+renesas@glider.be
2024-06-24clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in commentsGeert Uytterhoeven1-3/+3
The multipliers for PLL2 and PLL4 as listed in the comments for the cpg_pll_configs[] array are incorrect. Fix them. Note that the actual values in the tables were correct. Fixes: f077cab34df3010d ("clk: renesas: cpg-mssr: Add support for R-Car V4M") Reported-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Reviewed-by: Niklas Söderlund <[email protected]> Link: https://lore.kernel.org/07126b55807c1596422c9547e72f0a032487da1e.1718177076.git.geert+renesas@glider.be
2024-06-11clk: renesas: r8a779h0: Add VIN clocksNiklas Söderlund1-0/+16
Add the VIN module clocks, which are used by the VIN modules on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Niklas Söderlund <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-06-07clk: renesas: rcar-gen2: Use DEFINE_SPINLOCK() for static spinlockGeert Uytterhoeven1-3/+1
A static spinlock can be initialized automatically with DEFINE_SPINLOCK() rather than explicitly calling spin_lock_init(). Suggested-by: Ye Bin <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/8da2c908f00043f05f7e26e3c26400aea0cfe8bc.1716975021.git.geert+renesas@glider.be
2024-06-07clk: renesas: cpg-lib: Use DEFINE_SPINLOCK() for global spinlockGeert Uytterhoeven3-5/+1
A global spinlock can be initialized automatically with DEFINE_SPINLOCK() rather than explicitly calling spin_lock_init(). Suggested-by: Ye Bin <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/9073a6bfb7791e492156331fa8a0ea87a7c7cef6.1716975021.git.geert+renesas@glider.be
2024-06-07clk: renesas: r8a77970: Use common cpg_lockGeert Uytterhoeven1-4/+1
R-Car Gen3 Socs use the common CPG/MSSR library functions in rcar-cpg-lib.c, so the R-Car V3M sub-driver can use the common cpg_lock instead of a driver-private lock. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/0cd9b5ffbe986bd7dc4ffb3f13492123432ee2e1.1716975021.git.geert+renesas@glider.be
2024-06-03clk: renesas: r8a779h0: Add CSI-2 clocksNiklas Söderlund1-0/+2
Add the CSI40 and CSI41 module clocks, which are used by the CSI-2 interfaces on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Niklas Söderlund <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-06-03clk: renesas: r8a779h0: Add ISPCS clocksNiklas Söderlund1-0/+2
Add the ISPCS0 and ISPCS1 module clocks, which are used by the ISPCS modules on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Niklas Söderlund <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-04-25clk: renesas: r9a08g045: Add support for power domainsClaudiu Beznea1-0/+41
Instantiate power domains for the currently enabled IPs of the R9A08G045 SoC. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Ulf Hansson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-04-25clk: renesas: rzg2l: Extend power domain supportClaudiu Beznea2-14/+252
RZ/{G2L, V2L, G3S}-based CPG versions have support for saving extra power when clocks are disabled by activating module standby. This is done through MSTOP-specific registers that are part of CPG. Each individual module has one or more bits associated with one MSTOP register (see table "Registers for Module Standby Mode" from HW manuals). Hardware manual associates modules' clocks with one or more MSTOP bits. There are 3 mappings available (identified by researching RZ/G2L, RZ/G3S, RZ/V2L HW manuals): case 1: N clocks mapped to N MSTOP bits (with N={0, ..., X}) case 2: N clocks mapped to 1 MSTOP bit (with N={0, ..., X}) case 3: N clocks mapped to M MSTOP bits (with N={0, ..., X}, M={0, ..., Y}) Case 3 has been currently identified on RZ/V2L for the VCPL4 module. To cover all three cases, the individual platform drivers will provide the clock driver with MSTOP register offsets and associated bits in this register as a bitmask, and the clock driver will apply this bitmask to the proper MSTOP register. The MSTOP support was implemented through power domains. Platform-specific clock drivers will register an array of type struct rzg2l_cpg_pm_domain_init_data, which will be used to instantiate properly the power domains. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Ulf Hansson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-04-25clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INITGeert Uytterhoeven3-6/+0
CLK_ENABLE_ON_INIT is a relic from the old SH clock framework. It is not used on SH/R-Mobile ARM drivers. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/f01e60a1007afe9385ddc10c4665752857ba4135.1714032122.git.geert+renesas@glider.be
2024-04-25clk: renesas: r8a7740: Remove unused div4_clk.flags fieldChristophe JAILLET1-13/+12
In "struct div4_clk", the "flags" field is unused. Remove it, and update the "div4_clks" array accordingly. Found with cppcheck, unusedStructMember. Signed-off-by: Christophe JAILLET <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Tested-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/658e6b1b23d5b66646bb830361b8c55ccf797771.1713025170.git.christophe.jaillet@wanadoo.fr Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-04-23clk: renesas: r9a07g043: Add clock and reset entry for PLICLad Prabhakar1-0/+9
Add the missing clock and reset entry for PLIC. Also add R9A07G043_NCEPLIC_ACLK to the critical clocks list. Fixes: 95d48d270305ad2c ("clk: renesas: r9a07g043: Add support for RZ/Five SoC") Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
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