aboutsummaryrefslogtreecommitdiff
path: root/drivers/clk/renesas
AgeCommit message (Expand)AuthorFilesLines
2022-05-05clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Co...Biju Das1-0/+18
2022-05-05clk: renesas: r9a07g044: Add DSI clock and reset entriesBiju Das1-1/+16
2022-05-05clk: renesas: r9a07g044: Add LCDC clock and reset entriesBiju Das1-1/+8
2022-05-05clk: renesas: r9a07g044: Add M4 Clock supportBiju Das1-1/+18
2022-05-05clk: renesas: r9a07g044: Add M3 Clock supportBiju Das1-1/+4
2022-05-05clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks supportBiju Das1-1/+4
2022-05-05clk: renesas: r9a07g044: Add M1 clock supportBiju Das1-1/+10
2022-05-05clk: renesas: rzg2l: Add DSI divider clk supportBiju Das2-0/+136
2022-05-05clk: renesas: rzg2l: Add PLL5_4 clk mux supportBiju Das2-0/+103
2022-05-05clk: renesas: rzg2l: Add FOUTPOSTDIV clk supportBiju Das2-0/+235
2022-04-29clk: renesas: cpg-mssr: Add support for R-Car V4HYoshihiro Shimoda5-0/+231
2022-04-29clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4Yoshihiro Shimoda4-16/+24
2022-04-28clk: renesas: r9a07g043: Add WDT clock and reset entriesBiju Das1-0/+10
2022-04-28clk: renesas: r9a07g043: Add OSTM clock and reset entriesBiju Das1-0/+9
2022-04-28clk: renesas: r9a07g043: Add clock and reset entries for CANFDBiju Das1-0/+5
2022-04-28clk: renesas: r9a07g043: Add USB clocks/resetsBiju Das1-0/+12
2022-04-28clk: renesas: r9a07g043: Add SSIF-2 clock and reset entriesBiju Das1-0/+20
2022-04-28clk: renesas: r9a07g043: Add I2C clocks/resetsBiju Das1-0/+12
2022-04-28clk: renesas: r9a06g032: Fix the RTC hclock descriptionMiquel Raynal1-1/+1
2022-04-25clk: renesas: r8a779f0: Add UFS clockYoshihiro Shimoda1-0/+1
2022-04-13clk: renesas: r9a07g043: Add SDHI clock and reset entriesBiju Das1-0/+35
2022-04-13clk: renesas: r9a07g043: Add GbEthernet clock/resetBiju Das1-0/+10
2022-04-13clk: renesas: r9a07g043: Add ethernet clock sourcesBiju Das1-0/+13
2022-04-13clk: renesas: r9a07g043: Add GPIO clock and reset entriesBiju Das1-0/+5
2022-04-13clk: renesas: Add support for RZ/G2UL SoCBiju Das5-1/+171
2022-04-13clk: renesas: Move RPC core clocksGeert Uytterhoeven12-57/+51
2022-04-13clk: renesas: rzg2l: Simplify multiplication/shift logicGeert Uytterhoeven1-1/+1
2022-04-11clk: renesas: r8a77995: Add RPC clocksGeert Uytterhoeven2-1/+13
2022-04-11clk: renesas: r8a77990: Add RPC clocksGeert Uytterhoeven1-0/+9
2022-04-04clk: renesas: rzg2l: Remove unused notifiersPhil Edworthy1-2/+0
2022-02-22clk: renesas: r8a779f0: Add PFC clockGeert Uytterhoeven1-0/+1
2022-02-22clk: renesas: r8a779f0: Add I2C clocksGeert Uytterhoeven1-0/+6
2022-02-22clk: renesas: r8a779f0: Add WDT clockGeert Uytterhoeven1-0/+9
2022-02-22clk: renesas: r8a779f0: Fix RSW2 clock dividerGeert Uytterhoeven1-1/+1
2022-02-10clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoCBiju Das5-191/+250
2022-01-24clk: renesas: r8a779a0: Add CANFD module clockUlrich Hecht1-0/+1
2022-01-24clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3Lad Prabhakar1-2/+2
2022-01-24clk: renesas: r8a7799[05]: Add MLP clocksNikita Yushchenko2-0/+2
2022-01-24clk: renesas: r8a779f0: Add SYS-DMAC clocksYoshihiro Shimoda1-0/+2
2021-12-08clk: renesas: r9a07g044: Add GPU clock and reset entriesBiju Das1-0/+9
2021-12-08clk: renesas: r9a07g044: Add mux and divider for G clockBiju Das2-0/+10
2021-12-08clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macroBiju Das1-2/+2
2021-12-08clk: renesas: cpg-mssr: Add support for R-Car S4-8Yoshihiro Shimoda5-0/+196
2021-12-08clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driverYoshihiro Shimoda7-341/+437
2021-11-26clk: renesas: r9a07g044: Add TSU clock and reset entryBiju Das1-0/+3
2021-11-19clk: renesas: cpg-mssr: propagate return value of_genpd_add_provider_simple()Lad Prabhakar1-2/+1
2021-11-19clk: renesas: cpg-mssr: Check return value of pm_genpd_init()Lad Prabhakar1-1/+14
2021-11-19clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple()Lad Prabhakar1-2/+1
2021-11-19clk: renesas: rzg2l: Check return value of pm_genpd_init()Lad Prabhakar1-1/+13
2021-11-19clk: renesas: r9a07g044: Add RSPI clock and reset entriesLad Prabhakar1-0/+9