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A variable pointing to const isn't const itself. It has to contain
"const" keyword after "*" too. So to keep it in __initconst (and not
mark properly as __initdata), add the "const" keyword exactly there.
Note we need to update struct pistachio_mux too. On the other hand, the
clk core already counts with "const char *const" already.
[js] more explanatory commit message.
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: Martin Liska <[email protected]>
Signed-off-by: Andi Kleen <[email protected]>
Signed-off-by: Jiri Slaby <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Now that clk_register_mux_table takes a const u32 *, we can declare the
mux table as const u32[].
Signed-off-by: Jonathan Neuschäfer <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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We're moving pistachio to generic MIPS kernel. The clk driver
should be avilable to the generic MIPS kernel.
Signed-off-by: Jiaxun Yang <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Signed-off-by: Thomas Bogendoerfer <[email protected]>
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Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms and conditions of the gnu general public license
version 2 as published by the free software foundation
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 101 file(s).
Signed-off-by: Thomas Gleixner <[email protected]>
Reviewed-by: Allison Randal <[email protected]>
Cc: [email protected]
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Add SPDX license identifiers to all Make/Kconfig files which:
- Have no license information of any form
These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:
GPL-2.0-only
Signed-off-by: Thomas Gleixner <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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These clk_ops structures are only stored in the ops field of a
clk_init_data structure. This field is const, so the clk_ops
structures can be const as well.
Identified and transformed using Coccinelle.
Signed-off-by: Julia Lawall <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Current critical clock list for pistachio enables
only mips and sys clocks by default but there are
also other clocks that are not claimed by anyone and
needs to be enabled by default.
This patch updates the critical clocks that need
to be enabled by default.
Add a separate struct to distinguish the critical clocks
as listed:
1.) core clocks:
a.) mips clock
2.) peripheral system clocks:
a.) sys clock
b.) sys_bus clock
c.) DDR clock
d.) ROM clock
Fixes: b35d7c33419c("CLK: Pistachio: Register core clocks")
Cc: <[email protected]> # 4.1
Reviewed-by: Andrew Bresticker <[email protected]>
Signed-off-by: Ezequiel Garcia <[email protected]>
Signed-off-by: Damien.Horsley <[email protected]>
Signed-off-by: Govindraj Raja <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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.recalc_rate callback for the fractional PLL doesn't take operating
mode into account when calculating PLL rate. This results in
the incorrect PLL rates when PLL is operating in integer mode.
Operating mode of fractional PLL is based on the value of the
fractional divider. Currently it assumes that the PLL will always
be configured in fractional mode which may not be
the case. This may result in the wrong output frequency.
Also vco was calculated based on the current operating mode which
makes no sense because .set_rate is setting operating mode. Instead,
vco should be calculated using PLL settings that are about to be set.
Fixes: 43049b0c83f17("CLK: Pistachio: Add PLL driver")
Cc: <[email protected]> # 4.1
Reviewed-by: Andrew Bresticker <[email protected]>
Signed-off-by: Zdenko Pulitika <[email protected]>
Signed-off-by: Govindraj Raja <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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PLL enable callbacks are overriding PLL mode (int/frac) and
Noise reduction (on/off) settings set by the boot loader which
results in the incorrect clock rate.
PLL mode and noise reduction are defined by the DSMPD and DACPD bits
of the PLL control register. PLL .enable() callbacks enable PLL
by deasserting all power-down bits of the PLL control register,
including DSMPD and DACPD bits, which is not necessary since
these bits don't actually enable/disable PLL.
This commit fixes the problem by removing DSMPD and DACPD bits
from the "PLL enable" mask.
Fixes: 43049b0c83f17("CLK: Pistachio: Add PLL driver")
Cc: <[email protected]> # 4.1
Reviewed-by: Andrew Bresitcker <[email protected]>
Signed-off-by: Zdenko Pulitika <[email protected]>
Signed-off-by: Govindraj Raja <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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This commit fixes 32bit integer overflows throughout the pll driver
(i.e. wherever the result of integer multiplication may exceed the
range of u32).
One of the functions affected by this problem is .recalc_rate. It
returns incorrect rate for some pll settings (not for all though)
which in turn results in the incorrect rate setup of pll's child
clocks.
Fixes: 43049b0c83f17("CLK: Pistachio: Add PLL driver")
Cc: <[email protected]> # 4.1
Reviewed-by: Andrew Bresticker <[email protected]>
Signed-off-by: Zdenko Pulitika <[email protected]>
Signed-off-by: Govindraj Raja <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Use the provider based method to get a clock's name so that we
can get rid of the clk member in struct clk_hw one day. Mostly
converted with the following coccinelle script.
@@
struct clk_hw *E;
@@
-__clk_get_name(E->clk)
+clk_hw_get_name(E)
Acked-by: Heiko Stuebner <[email protected]>
Cc: Sylwester Nawrocki <[email protected]>
Cc: Tomasz Figa <[email protected]>
Cc: Peter De Schrijver <[email protected]>
Cc: Prashant Gaikwad <[email protected]>
Cc: Stephen Warren <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Cc: Thierry Reding <[email protected]>
Cc: Alexandre Courbot <[email protected]>
Cc: Tero Kristo <[email protected]>
Cc: Ulf Hansson <[email protected]>
Acked-by: Sebastian Hesselbarth <[email protected]>
Acked-by: Andrew Bresticker <[email protected]>
Cc: Ezequiel Garcia <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: Kevin Cernekee <[email protected]>
Acked-by: Geert Uytterhoeven <[email protected]>
Cc: Ulrich Hecht <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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This clock provider uses the consumer API, so include clk.h
explicitly.
Cc: Andrew Bresticker <[email protected]>
Cc: Ralf Baechle <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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When setting the PLL rates, check that:
- VCO is within range
- PFD is within range
- PLL is disabled when postdiv is changed
- postdiv2 <= postdiv1
Reviewed-by: Andrew Bresticker <[email protected]>
Signed-off-by: Kevin Cernekee <[email protected]>
Signed-off-by: Ezequiel Garcia <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Currently, when the rate is changed, the driver makes sure the
PLL is enabled before doing so. This is done because the PLL
cannot be locked while disabled. Once locked, the drivers
returns the PLL to its previous enable/disable state.
This is a bit cumbersome, and can be simplified.
This commit reworks the .set_rate() functions for the integer
and fractional PLLs. Upon rate change, the PLL is now locked
only if it's already enabled.
Also, the driver locks the PLL on .enable(). This makes sure
the PLL is locked when enabled, and not locked when disabled.
Signed-off-by: Andrew Bresticker <[email protected]>
Signed-off-by: Ezequiel Garcia <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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This commit adds a pll_lock() helper making the code more readable.
Cosmetic change only, no functionality changes.
Signed-off-by: Andrew Bresticker <[email protected]>
Signed-off-by: Ezequiel Garcia <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Register the clock gates for the external audio and ethernet
reference clocks provided by the top-level general control block.
Signed-off-by: Damien Horsley <[email protected]>
Signed-off-by: Andrew Bresticker <[email protected]>
Cc: Mike Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Ezequiel Garcia <[email protected]>
Cc: James Hartley <[email protected]>
Cc: James Hogan <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/9321/
Signed-off-by: Ralf Baechle <[email protected]>
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Register the system interface gate clocks provided by the peripheral
general control block. These clocks gate register access for various
peripherals.
Signed-off-by: Damien Horsley <[email protected]>
Signed-off-by: Andrew Bresticker <[email protected]>
Cc: Mike Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Ezequiel Garcia <[email protected]>
Cc: James Hartley <[email protected]>
Cc: James Hogan <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/9322/
Signed-off-by: Ralf Baechle <[email protected]>
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Register the clocks generated by the peripheral clock controller.
This includes the clocks for several peripherals, including I2C,
PWM, watchdog, and timer.
Signed-off-by: Damien Horsley <[email protected]>
Signed-off-by: Andrew Bresticker <[email protected]>
Cc: Mike Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Ezequiel Garcia <[email protected]>
Cc: James Hartley <[email protected]>
Cc: James Hogan <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/9320/
Signed-off-by: Ralf Baechle <[email protected]>
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Register the clocks generated by the core clock controller.
This includes the 7 PLLs and clocks for the CPU, RPU co-processor,
audio, WiFi, bluetooth, and several other peripherals.
The MIPS and PERIPH_SYS clocks must remain enabled at all times.
Signed-off-by: Damien Horsley <[email protected]>
Signed-off-by: Andrew Bresticker <[email protected]>
Cc: Mike Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Ezequiel Garcia <[email protected]>
Cc: James Hartley <[email protected]>
Cc: James Hogan <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/9317/
Signed-off-by: Ralf Baechle <[email protected]>
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Add a driver for the integer (GF40LP_LAINT) and fractional (GF40LP_FRAC)
PLLs present on Pistachio.
Signed-off-by: Andrew Bresticker <[email protected]>
Cc: Mike Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Ezequiel Garcia <[email protected]>
Cc: James Hartley <[email protected]>
Cc: James Hogan <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/9316/
Signed-off-by: Ralf Baechle <[email protected]>
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Add helpers for registering clocks and clock providers on Pistachio.
Signed-off-by: Andrew Bresticker <[email protected]>
Cc: Mike Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Ezequiel Garcia <[email protected]>
Cc: James Hartley <[email protected]>
Cc: James Hogan <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/9318/
Signed-off-by: Ralf Baechle <[email protected]>
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