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2024-06-04clk: meson: c3: add c3 clock peripherals controller driverXianwei Zhao1-0/+1
Add the C3 peripherals clock controller driver in the C3 SoC family. [jbrunet: fix Kconfig select order and probe function name] Co-developed-by: Chuan Liu <[email protected]> Signed-off-by: Chuan Liu <[email protected]> Signed-off-by: Xianwei Zhao <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jerome Brunet <[email protected]>
2024-06-04clk: meson: c3: add support for the C3 SoC PLL clockXianwei Zhao1-0/+1
Add the C3 PLL clock controller driver for the Amlogic C3 SoC family. [jbrunet: fixed probe function name] Co-developed-by: Chuan Liu <[email protected]> Signed-off-by: Chuan Liu <[email protected]> Signed-off-by: Xianwei Zhao <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jerome Brunet <[email protected]>
2024-04-10clk: meson: add vclk driverNeil Armstrong1-0/+1
The VCLK and VCLK_DIV clocks have supplementary bits. The VCLK gate has a "SOFT RESET" bit to toggle after the whole VCLK sub-tree rate has been set, this is implemented in the gate enable callback. The VCLK_DIV clocks as enable and reset bits used to disable and reset the divider, associated with CLK_SET_RATE_GATE it ensures the rate is set while the divider is disabled and in reset mode. The VCLK_DIV enable bit isn't implemented as a gate since it's part of the divider logic and vendor does this exact sequence to ensure the divider is correctly set. Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-2-99ecdfdc87fc@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-09-27clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controllerYu Tu1-0/+1
Add the peripherals clock controller driver in the S4 SoC family. [jbrunet: remove extra new line at end of s4-peripherals.h] Signed-off-by: Yu Tu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jerome Brunet <[email protected]>
2023-09-27clk: meson: S4: add support for Amlogic S4 SoC PLL clock driverYu Tu1-0/+1
Add the S4 PLL clock controller driver in the S4 SoC family. Signed-off-by: Yu Tu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08clk: meson: introduce meson-clkc-utilsNeil Armstrong1-0/+1
Let's introduce a new module called meson-clkc-utils that will contain shared utility functions for all Amlogic clock controller drivers. The first utility function is a replacement of of_clk_hw_onecell_get in order to get rid of the NR_CLKS define in all Amlogic clock drivers. The goal is to move all duplicate probe and init code in this module. [jbrunet: Fixed MODULE_LICENCE checkpatch warning] Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-1-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-05-30clk: meson: a1: add Amlogic A1 Peripherals clock controller driverDmitry Rokosov1-0/+1
Introduce Peripherals clock controller for Amlogic A1 SoC family. A1 SoC has four clock controllers on the board: PLL, Peripherals, CPU, and Audio. This patchset adds support for Amlogic A1 Peripherals clock driver and allows to generate clocks for all A1 SoC peripheral IPs. Signed-off-by: Jian Hu <[email protected]> Signed-off-by: Dmitry Rokosov <[email protected]> Reviewed-by: Martin Blumenstingl <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jerome Brunet <[email protected]>
2023-05-30clk: meson: a1: add Amlogic A1 PLL clock controller driverDmitry Rokosov1-0/+1
Introduce PLL clock controller for Amlogic A1 SoC family. The clock unit is an APB slave module that is designed for generating all of the internal and system clocks. The SoC uses an external 24MHz crystal; there are 4 internal PLLs: SYS_PLL/HIFI_PLL/USB_PLL/(FIXPLL), these PLLs generate 27 clock sources. Signed-off-by: Jian Hu <[email protected]> Signed-off-by: Dmitry Rokosov <[email protected]> Reviewed-by: Martin Blumenstingl <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jerome Brunet <[email protected]>
2019-12-11clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controllerMartin Blumenstingl1-1/+1
The Meson8/Meson8b/Meson8m2 SoCs embed a DDR clock controller in the MMCBUS registers. There is no public documentation, but the u-boot GPL sources from the Amlogic BSP show that the DDR clock controller is identical on all three SoCs: #define CFG_DDR_CLK 792 #define CFG_PLL_M (((CFG_DDR_CLK/12)*12)/24) #define CFG_PLL_N 1 #define CFG_PLL_OD 1 // from set_ddr_clock: t_ddr_pll_cntl= (CFG_PLL_OD << 16)|(CFG_PLL_N<<9)|(CFG_PLL_M<<0) writel(timing_reg->t_ddr_pll_cntl|(1<<29),AM_DDR_PLL_CNTL); writel(readl(AM_DDR_PLL_CNTL) & (~(1<<29)),AM_DDR_PLL_CNTL); // from hx_ddr_power_down_enter: shut down DDR PLL writel(readl(AM_DDR_PLL_CNTL)|(1<<30),AM_DDR_PLL_CNTL); do { ... } while((readl(AM_DDR_PLL_CNTL)&(1<<31))==0) This translates to: - AM_DDR_PLL_CNTL[29] is the reset bit - AM_DDR_PLL_CNTL[30] is the enable bit - AM_DDR_PLL_CNTL[31] is the lock bit - AM_DDR_PLL_CNTL[8:0] is the m value (assuming the width is 9 bits based on the start of the n value) - AM_DDR_PLL_CNTL[13:9] is the n value (assuming the width is 5 bits based on the start of the od) - AM_DDR_PLL_CNTL[17:16] is the od (assuming the width is 2 bits based on other PLLs on this SoC) Add a driver for this PLL setup because it's used as one of the inputs of the audio clocks. There may be more clocks inside that clock controller - those can be added in subsequent patches. Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2019-08-09clk: meson: add g12a cpu dynamic divider driverNeil Armstrong1-0/+1
Add a clock driver for the cpu dynamic divider, this divider needs to have a flag set before setting the divider value then removed while writing the new value to the register. This drivers implements this behavior and will be used essentially on the Amlogic G12A and G12B SoCs for cpu clock trees. Signed-off-by: Neil Armstrong <[email protected]> Reviewed-by: Martin Blumenstingl <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2019-07-29clk: meson: remove clk input helperAlexandre Mergnat1-1/+0
The clk input function which allows clock controllers to register a bypass clock from a clock producer is no longer needed anymore since meson clock controllers have migrated to a new parent allocation method. Signed-off-by: Alexandre Mergnat <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner1-0/+1
Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-02-13clk: meson: Add G12A AO Clock + Reset ControllerNeil Armstrong1-1/+1
Add the Amlogic G12A AO Clock and Reset controller driver handling generation of Always-On clocks : - AO Clocks and Reset for Always-On modules - 32K Generation for USB and CEC - SAR ADC controller clock Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Jerome Brunet <[email protected]> Acked-by: Jerome Brunet <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2019-02-04clk: meson: factorise meson64 peripheral clock controller driversJerome Brunet1-0/+1
The function used to probe the peripheral clock controller of the arm64 amlogic SoCs is mostly the same. We now have 3 of those controllers so it is time to factorize things a bit. Signed-off-by: Jerome Brunet <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2019-02-04clk: meson: g12a: add peripheral clock controllerJian Hu1-0/+1
Add the peripheral clock controller found in the g12a SoC family Signed-off-by: Jian Hu <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Jerome Brunet <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2019-02-02clk: meson: rework and clean drivers dependenciesJerome Brunet1-11/+16
Initially, the meson clock directory only hosted 2 controllers drivers, for meson8 and gxbb. At the time, both used the same set of clock drivers so managing the dependencies was not a big concern. Since this ancient time, entropy did its job, controllers with different requirement and specific clock drivers have been added. Unfortunately, we did not do a great job at managing the dependencies between the controllers and the different clock drivers. Some drivers, such as clk-phase or vid-pll-div, are compiled even if they are useless on the target (meson8). As we are adding new controllers, we need to be able to pick a driver w/o pulling the whole thing. The patch aims to clean things up by: * providing a dedicated CONFIG_ for each clock drivers * allowing clock drivers to be compiled as a modules, if possible * stating explicitly which drivers are required by each controller. Signed-off-by: Jerome Brunet <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2019-01-07clk: meson: gxbb-ao: replace cec-32k with the dual dividerJerome Brunet1-1/+1
Replace the cec-32k clock of gxbb-ao with the simpler dual divider driver. The dual divider implements only the dividing part. All the other bits are now exposed using simple elements, such as gates and muxes Signed-off-by: Jerome Brunet <[email protected]> Acked-by: Neil Armstrong <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2019-01-07clk: meson: add dual divider clock driverJerome Brunet1-1/+1
Add the dual divider driver. This special divider make a weighted average between 2 dividers to reach fractional divider values. Signed-off-by: Jerome Brunet <[email protected]> Acked-by: Neil Armstrong <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2018-12-05clk: meson: add clk-input helper functionJerome Brunet1-0/+1
Add the clock input helper function. Several amlogic clock controllers will now be registering bypass clock input. Instead of copying this code in every of them, let's make an helper function for it Signed-off-by: Jerome Brunet <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> [narmstrong: fixed up to apply on Makefile and clkc.h] Signed-off-by: Neil Armstrong <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2018-11-23clk: meson: Add vid_pll divider driverNeil Armstrong1-1/+1
Add support the VID_PLL fully programmable divider used right after the HDMI PLL clock source. It is used to achieve complex fractional division with a programmble bitfield. Signed-off-by: Neil Armstrong <[email protected]> Acked-by: Jerome Brunet <[email protected]> Link: http://lkml.kernel.org/r/[email protected]
2018-07-09clk: meson: remove unused clk-audio-divider driverJerome Brunet1-2/+1
clk-audio-divider is no longer used, we can remove it. Acked-by: Neil Armstrong <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-07-09clk: meson: axg: add the audio clock controller driverJerome Brunet1-0/+1
The axg audio clock controller is the clock generation unit for the amlogic audio subsystem of A113 based SoCs. It may be clocked by 8 different plls provided by the primary clock controller and also by 10 slave bit clocks and 10 slave sample clocks which may be provided by external components, such as audio codecs, through the SoC pads. It contains several muxes, dividers and gates which are fed into the the different devices of the audio subsystem. Acked-by: Neil Armstrong <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-07-09clk: meson: add axg audio sclk divider driverJerome Brunet1-1/+1
Add a driver to control the clock divider found in the sample clock generator of the axg audio clock controller. The sclk divider accumulates specific features which make the generic divider unsuitable to control it: - zero based divider (div = val + 1), but zero value gates the clock, so minimum divider value is 2. - lrclk variant may adjust the duty cycle depending the divider value and the 'hi' value. Acked-by: Neil Armstrong <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-07-09clk: meson: add triple phase clock driverJerome Brunet1-0/+1
Add a driver to control the output of the sample clock generator found in the axg audio clock controller. The goal of this driver is to coherently control the phase provided to the different element using the sample clock generator. This simplify the usage of the sample clock generator a lot, without comprising the ability of the SoC. Acked-by: Neil Armstrong <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-07-09clk: meson: add clk-phase clock driverJerome Brunet1-0/+1
Add a driver based meson clk-regmap to control clock phase on amlogic SoCs Acked-by: Neil Armstrong <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-05-15clk: meson-axg: Add AO Clock and Reset controller driverQiufang Dai1-1/+1
Adds a Clock and Reset controller driver for the Always-On part of the Amlogic Meson-AXG SoC. Signed-off-by: Qiufang Dai <[email protected]> Signed-off-by: Yixun Lan <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-05-15clk: meson: aoclk: refactor common code into dedicated fileYixun Lan1-0/+1
We try to refactor the common code into one dedicated file, while preparing to add new Meson-AXG aoclk driver, this would help us to better share the code by all aoclk drivers. Suggested-by: Jerome Brunet <[email protected]> Signed-off-by: Yixun Lan <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-03-13clk: meson: remove obsolete cpu_clkJerome Brunet1-1/+1
meson8b cpu_clk has been replaced by a set of divider and mux clocks. meson_cpu_clk is no longer used and can be removed Acked-by: Martin Blumenstingl <[email protected]> Signed-off-by: Jerome Brunet <[email protected]> Signed-off-by: Neil Armstrong <[email protected]>
2018-03-13clk: meson: switch gxbb ao_clk to clk_regmapJerome Brunet1-1/+1
Drop the gxbb ao specific regmap based clock and use the meson clk_regmap based clock instead. Signed-off-by: Jerome Brunet <[email protected]> Signed-off-by: Neil Armstrong <[email protected]>
2018-03-13clk: meson: add regmap clocksJerome Brunet1-0/+1
Meson clock controllers need to move the classical iomem registers to regmap. This is triggered because the HHI controllers found on the GXBB and GXL host more than just clocks. To properly handle this, we would like to migrate HHI to syscon. Also GXBB AO clock controller already use regmap, AXG AO and Audio clock controllers will as well. The purpose of this change is to provide a common structure to these meson controllers (and possibly others) for regmap based clocks. This change provides the basic gate, mux and divider, based on the helpers provided by the related generic clocks Signed-off-by: Jerome Brunet <[email protected]> Signed-off-by: Neil Armstrong <[email protected]>
2017-12-14clk: meson-axg: add clock controller driversQiufang Dai1-0/+1
Add clock controller drivers for Amlogic Meson-AXG SoC. Acked-by: Neil Armstrong <[email protected]> Signed-off-by: Qiufang Dai <[email protected]> Signed-off-by: Yixun Lan <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2017-08-04clk: meson: gxbb-aoclk: Add CEC 32k clockNeil Armstrong1-1/+1
The CEC 32K AO Clock is a dual divider with dual counter to provide a more precise 32768Hz clock for the CEC subsystem from the external xtal. Signed-off-by: Neil Armstrong <[email protected]>
2017-08-04clk: meson: gxbb-aoclk: Switch to regmap for register accessNeil Armstrong1-1/+1
Switch the aoclk driver to use the new bindings and switch all the registers access to regmap only. Signed-off-by: Neil Armstrong <[email protected]>
2017-04-07clk: meson: add audio clock divider supportJerome Brunet1-1/+1
The audio divider needs a specific clock divider driver. With am mpll parent clock, which is able to provide a fairly precise rate, the generic divider tends to select low value of the divider. In such case the quality of the clock is very poor. For the same final rate, maximizing the audio clock divider value and selecting the corresponding mpll rate gives better results. This is what this driver aims to acheive. So far, so good. Cc: Hendrik v. Raven <[email protected]> Acked-by: Michael Turquette <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2016-09-01clk: meson: Rename meson8b-clkc.c to reflect gxbb naming conventionAlexander Müller1-1/+1
Signed-off-by: Alexander Müller <[email protected]> Signed-off-by: Michael Turquette <[email protected]> Link: lkml.kernel.org/r/[email protected]
2016-08-19clk: meson: Add GXBB AO Clock and Reset controller driverNeil Armstrong1-1/+1
Adds a Clock and Reset controller driver for the Always-On part of the Amlogic Meson GXBB SoC. It exports paired Clocks and Resets lines that will be used by peripherals in the Always-On subsystem. Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2016-06-22clk: gxbb: add AmLogic GXBB clk controller driverMichael Turquette1-0/+1
The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <[email protected]> Signed-off-by: Michael Turquette <[email protected]>
2016-06-22clk: meson: add mpll supportMichael Turquette1-1/+1
MPLLs are adjustable rate clocks derived from PLLs. On both Meson8b and GXBB they appear to be only derived from fixed_pll. Add support for these clock types so that they can be added to their respective drivers. Tested-by: Kevin Hilman <[email protected]> Signed-off-by: Michael Turquette <[email protected]>
2016-06-22clk: meson: only build selected platformsMichael Turquette1-2/+2
Break the AmLogic clock code up so that only the necessary parts are compiled and linked. The core code is selected by both arm and arm64 builds with COMMON_CLK_AMLOGIC. The individual drivers have their own config options as well. Tested-by: Kevin Hilman <[email protected]> Signed-off-by: Michael Turquette <[email protected]>
2016-06-22clk: meson8b: clean up composite clocksMichael Turquette1-1/+1
Remove the composite clock registration function and helpers. Replace unnecessary configuration struct with static initialization of the desired clock type. To preserve git bisect this patch also flips the switch and starts using of_clk_add_hw_provider instead of the deprecated meson_clk_register_clks method. As a byproduct clk.c can be deleted. Tested-by: Kevin Hilman <[email protected]> Signed-off-by: Michael Turquette <[email protected]>
2015-06-05clk: meson8b: Add support for Meson8b clocksCarlo Caione1-0/+1
This patch adds support for the basic clocks found on the Amlogic Meson8b SoCs. Signed-off-by: Carlo Caione <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-06-05clk: meson: Add support for Meson clock controllerCarlo Caione1-0/+5
This patchset adds the infrastructure for registering and managing the core clocks found on Amlogic MesonX SoCs. In particular: - PLLs - CPU clock - Fixed rate clocks, fixed factor clocks, ... Signed-off-by: Carlo Caione <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
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