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2024-01-03clk: mediatek: add drivers for MT7988 SoCSam Shih1-0/+5
Add APMIXED, ETH, INFRACFG and TOPCKGEN clock drivers which are typical MediaTek designs. Also add driver for XFIPLL clock generating the 156.25MHz clock for the XFI SerDes. It needs an undocumented software workaround and has an unknown internal design. Signed-off-by: Sam Shih <[email protected]> Signed-off-by: Daniel Golle <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/c7574d808e2da1a530182f0fd790c1337c336e1b.1702849494.git.daniel@makrotopia.org [[email protected]: Add module license to infracfg file] Signed-off-by: Stephen Boyd <[email protected]>
2023-03-31clk: mediatek: Add MT8188 adsp clock supportGarmin.Chang1-0/+1
Add MT8188 adsp clock controller which provides clock gate control for Audio DSP. Signed-off-by: Garmin.Chang <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-03-31clk: mediatek: Add MT8188 imp i2c wrapper clock supportGarmin.Chang1-0/+1
Add MT8188 imp i2c wrapper clock controllers which provide clock gate control in I2C IP blocks. Signed-off-by: Garmin.Chang <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-03-31clk: mediatek: Add MT8188 wpesys clock supportGarmin.Chang1-0/+1
Add MT8188 wpesys clock controllers which provide clock gate control in Wrapping Engine. Signed-off-by: Garmin.Chang <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-03-31clk: mediatek: Add MT8188 vppsys1 clock supportGarmin.Chang1-1/+1
Add MT8188 vppsys1 clock controller which provides clock gate controller for Video Processor Pipe. Signed-off-by: Garmin.Chang <[email protected]> Reviewed-by: Matthias Brugger <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-03-31clk: mediatek: Add MT8188 vppsys0 clock supportGarmin.Chang1-0/+1
Add MT8188 vppsys0 clock controller which provides clock gate controller for Video Processor Pipe. Signed-off-by: Garmin.Chang <[email protected]> Reviewed-by: Matthias Brugger <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-03-31clk: mediatek: Add MT8188 vencsys clock supportGarmin.Chang1-0/+1
Add MT8188 vencsys clock controllers which provide clock gate control for video encoder. Signed-off-by: Garmin.Chang <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-03-31clk: mediatek: Add MT8188 vdosys1 clock supportGarmin.Chang1-1/+1
Add MT8188 vdosys1 clock controller which provides clock gate control in video system. This is integrated with mtk-mmsys driver which will populate device by platform_device_register_data to start vdosys clock driver. Signed-off-by: Garmin.Chang <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-03-31clk: mediatek: Add MT8188 vdosys0 clock supportGarmin.Chang1-0/+1
Add MT8188 vdosys0 clock controller which provides clock gate control in video system. This is integrated with mtk-mmsys driver which will populate device by platform_device_register_data to start vdosys clock driver. Signed-off-by: Garmin.Chang <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-03-31clk: mediatek: Add MT8188 vdecsys clock supportGarmin.Chang1-0/+1
Add MT8188 vdec clock controllers which provide clock gate control for video decoder. Signed-off-by: Garmin.Chang <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-03-31clk: mediatek: Add MT8188 mfgcfg clock supportGarmin.Chang1-0/+1
Add MT8188 mfg clock controller which provides clock gate control for GPU. Signed-off-by: Garmin.Chang <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-03-31clk: mediatek: Add MT8188 ipesys clock supportGarmin.Chang1-0/+1
Add MT8188 ipesys clock controller which provides clock gate control for Image Process Engine. Signed-off-by: Garmin.Chang <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-03-31clk: mediatek: Add MT8188 imgsys clock supportGarmin.Chang1-0/+1
Add MT8188 imgsys clock controllers which provide clock gate control for image IP blocks. Signed-off-by: Garmin.Chang <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-03-31clk: mediatek: Add MT8188 ccusys clock supportGarmin.Chang1-1/+1
Add MT8188 ccusys clock controller which provides clock gate control in Camera Computing Unit. Signed-off-by: Garmin.Chang <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-03-31clk: mediatek: Add MT8188 camsys clock supportGarmin.Chang1-0/+1
Add MT8188 camsys clock controllers which provide clock gate control for camera IP blocks. Signed-off-by: Garmin.Chang <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-03-31clk: mediatek: Add MT8188 infrastructure clock supportGarmin.Chang1-1/+1
Add MT8188 infrastructure clock controller which provides clock gate control for basic IP like pwm, uart, spi and so on. Signed-off-by: Garmin.Chang <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-03-31clk: mediatek: Add MT8188 peripheral clock supportGarmin.Chang1-1/+2
Add MT8188 peripheral clock controller which provides clock gate control for ethernet/flashif/pcie/ssusb. Signed-off-by: Garmin.Chang <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-03-31clk: mediatek: Add MT8188 topckgen clock supportGarmin.Chang1-1/+1
Add MT8188 topckgen clock controller which provides muxes, dividers to handle variety clock selection in other IP blocks. Signed-off-by: Garmin.Chang <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-03-31clk: mediatek: Add MT8188 apmixedsys clock supportGarmin.Chang1-0/+1
Add MT8188 apmixedsys clock controller which provides Plls generated from SoC 26m and ssusb clock gate control. Signed-off-by: Garmin.Chang <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-03-13clk: mediatek: mt8135: Move apmixedsys to its own fileAngeloGioacchino Del Regno1-1/+1
In preparation for migrating mt8135 clocks to the common simple probe mechanism, move the apmixedsys clocks to a different file. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/20230306140543.1813621-51-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <[email protected]>
2023-03-13clk: mediatek: mt8192: Move apmixedsys clock driver to its own fileAngeloGioacchino Del Regno1-1/+1
This is the last man standing in clk-mt8192.c that won't allow us to use the module_platform_driver() macro, and for *no* good reason. Move it to clk-mt8192-apmixedsys.c and while at it, also add a .remove() callback for it. Also, since the need for "clk-mt8192-simple" and "clk-mt8192" was just due to them being in the same file and probing different clocks, and since now there's just one platform_driver struct per file, it seemed natural to rename the `-simple` variant to just "clk-mt8192". Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Tested-by: Miles Chen <[email protected]> Tested-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/20230306140543.1813621-48-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <[email protected]>
2023-03-13clk: mediatek: Split configuration options for MT8186 clock driversAngeloGioacchino Del Regno1-5/+13
When building clock drivers for MT8186, some may want to build in only some of them to, for example, get CPUFreq up faster, and some may want to leave out some clock drivers entirely as a machine may not need the Warp Engine or the camera ISP (hence, their clock drivers). Split the various clock drivers in their own configuration options, keeping MT8186 configuration options consistent with other MediaTek SoCs. While at it, also allow building the remaining clock drivers as modules by switching COMMON_CLK_MT8186 to tristate. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/20230306140543.1813621-47-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <[email protected]>
2023-03-13clk: mediatek: Split MT8195 clock drivers and allow module buildAngeloGioacchino Del Regno1-7/+13
MT8195 clock drivers were encapsulated in one single (and big) Kconfig option: there's no reason to do that, as it is totally unnecessary to build in all or none of them. Split them out: keep boot-critical clocks as bool and allow choosing non critical clocks as tristate. As a note, the dependencies of VDEC/VENCSYS and CAM/IMG/IPE/WPESYS are not for build-time but rather for runtime, as clocks registered by those have runtime dependencies on either or both VPP and IMGSYS. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Tested-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/20230306140543.1813621-40-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <[email protected]>
2023-03-13clk: mediatek: mt8516: Move apmixedsys clock driver to its own fileAngeloGioacchino Del Regno1-1/+1
In preparation for migrating mt8516 clocks to the common simple probe mechanism, convert the apmixedsys to be a separated platform driver and move it to clk-mt8516-apmixedsys.c. While at it, also fix some indentation issues. During the conversion, error handling was added to the apmixedsys probe function. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/20230306140543.1813621-29-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <[email protected]>
2023-03-13clk: mediatek: mt7622: Move infracfg to clk-mt7622-infracfg.cAngeloGioacchino Del Regno1-1/+2
The infracfg driver cannot be converted to clk_mtk_simple_probe() as it registers cpumuxes, which is not supported on the common probing mechanism: for this reason, move it to its own file. While at it, also convert it to be a platform driver instead; to do so, also add a .remove() callback for this driver. During the conversion, error handling was added to the infracfg probe function. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/20230306140543.1813621-27-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <[email protected]>
2023-03-13clk: mediatek: mt7622: Move apmixedsys clock driver to its own fileAngeloGioacchino Del Regno1-1/+1
In preparation for migrating mt7622 clocks to the common simple probe mechanism, move apmixedsys clocks to a different file. While at it, use the builtin_platform_driver() macro for it. During the conversion, error handling was added to the apmixedsys probe function. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/20230306140543.1813621-25-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <[email protected]>
2023-03-13clk: mediatek: mt8183: Move apmixedsys clock driver to its own fileAngeloGioacchino Del Regno1-1/+1
In preparation for migrating all other mt8183 clocks to the common mtk_clk_simple_probe(), move apmixedsys clocks to a different file. While at it, use the builtin_platform_driver() macro for it and fix some indentation issues in the PLLs table. During the conversion, error handling was added to the apmixedsys probe function. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Tested-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/20230306140543.1813621-20-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <[email protected]>
2023-03-13clk: mediatek: mt8167: Move apmixedsys as platform_driver in new fileAngeloGioacchino Del Regno1-1/+1
In preparation for migrating all other MT8167 clocks to the common mtk_clk_simple_probe(), move apmixedsys clocks to a different file. While at it, also migrate away from the legacy CLK_OF_DECLARE and convert this clock driver to be a platform_driver instead. During the conversion, error handling was added to the apmixedsys probe function. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/20230306140543.1813621-17-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <[email protected]>
2023-03-13clk: mediatek: mt8365: Move apmixedsys clock driver to its own fileAngeloGioacchino Del Regno1-1/+1
In preparation for migrating all other mt8365 clocks to the common mtk_clk_simple_probe(), move apmixedsys clocks to a different file. While at it, use the builtin_platform_driver() macro for it. During the conversion, error handling was added to the apmixedsys probe function. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/20230306140543.1813621-12-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <[email protected]>
2023-03-13clk: mediatek: mt2712: Move apmixedsys clock driver to its own fileAngeloGioacchino Del Regno1-1/+1
The only clock driver that does not support mtk_clk_simple_probe() is apmixedsys: in preparation for enabling module build of non-critical mt2712 clocks, move this to its own file. While at it, also fix some indentation issues in the PLLs table. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-01-30clk: mediatek: add MT7981 clock supportDaniel Golle1-0/+4
Add MT7981 clock support, include topckgen, apmixedsys, infracfg and ethernet subsystem clocks. The drivers are based on clk-mt7981.c which can be found in MediaTek's SDK sources. To be fit for upstream inclusion the driver has been split into clock domains and the infracfg part has been significantly de-bloated by removing all the 1:1 factors (aliases). Signed-off-by: Jianhui Zhao <[email protected]> Signed-off-by: Daniel Golle <[email protected]> Link: https://lore.kernel.org/r/8136eb5b2049177bc2f6d3e0f2aefecc342d626f.1674703830.git.daniel@makrotopia.org Reviewed-by: AngeloGioacchino Del Regno <[email protected]> [[email protected]: Add module license] Signed-off-by: Stephen Boyd <[email protected]>
2023-01-30clk: mediatek: mt8173: Break down clock drivers and allow module buildAngeloGioacchino Del Regno1-1/+5
Split the giant clock driver for MT8173 into smaller drivers and make it possible to build the non boot critical clock controller drivers as modules by adding remove functions and both module description and license where needed. While at it, also change a mtk_register_reset_controller() call to mtk_register_reset_controller_with_dev() in mt8173-infracfg. Some spare code style cleanups were also performed. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Tested-by: Mingming Su <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2022-11-29clk: mediatek: Add new clock driver to handle FHCTL hardwareJohnson Wang1-0/+1
To implement frequency hopping and spread spectrum clocking function, we introduce new clock type and APIs to handle FHCTL hardware. Co-developed-by: Edward-JW Yang <[email protected]> Signed-off-by: Edward-JW Yang <[email protected]> Signed-off-by: Johnson Wang <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2022-09-30clk: mediatek: add driver for MT8365 SoCFabien Parent1-0/+7
Add clock drivers for MT8365 SoC. Signed-off-by: Fabien Parent <[email protected]> Signed-off-by: Markus Schneider-Pargmann <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reported-by: kernel test robot <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2022-09-26clk: mediatek: Add MediaTek Helio X10 MT6795 clock driversAngeloGioacchino Del Regno1-0/+6
Add the clock drivers for the entire clock tree of MediaTek Helio X10 MT6795, including system clocks (apmixedsys, infracfg, pericfg, topckgen) and multimedia clocks (mmsys, mfg, vdecsys, vencsys). Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Matthias Brugger <[email protected]> Reviewed-by: Miles Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2022-04-25clk: mediatek: Add MT8186 ipesys clock supportChun-Jie Chen1-1/+1
Add MT8186 ipesys clock controller which provides clock gate control for Image Process Engine. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Miles Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-04-25clk: mediatek: Add MT8186 mdpsys clock supportChun-Jie Chen1-1/+1
Add MT8186 mdpsys clock controller which provides clock gate control in Multimedia Data Path. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Miles Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-04-25clk: mediatek: Add MT8186 camsys clock supportChun-Jie Chen1-1/+2
Add MT8186 camsys clock controllers which provide clock gate control for camera IP blocks. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Miles Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-04-25clk: mediatek: Add MT8186 vencsys clock supportChun-Jie Chen1-1/+1
Add MT8186 vencsys clock controller which provide clock gate control for video encoder. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Miles Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-04-25clk: mediatek: Add MT8186 vdecsys clock supportChun-Jie Chen1-1/+1
Add MT8186 vdec clock controller which provide clock gate control for video decoder. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Miles Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-04-25clk: mediatek: Add MT8186 imgsys clock supportChun-Jie Chen1-1/+2
Add MT8186 imgsys clock controllers which provide clock gate control for image IP blocks. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Miles Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-04-25clk: mediatek: Add MT8186 wpesys clock supportChun-Jie Chen1-1/+1
Add MT8186 wpesys clock controllers which provide clock gate control in Wrapping Engine. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Miles Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-04-25clk: mediatek: Add MT8186 mmsys clock supportChun-Jie Chen1-1/+1
Add MT8186 mmsys clock controller which provides clock gate control in video system. This is integrated with mtk-mmsys driver which will populate device by platform_device_register_data to start mmsys clock driver. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Miles Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-04-25clk: mediatek: Add MT8186 mfgsys clock supportChun-Jie Chen1-1/+2
Add MT8186 mfg clock controller which provides clock gate control for GPU. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Miles Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-04-25clk: mediatek: Add MT8186 imp i2c wrapper clock supportChun-Jie Chen1-1/+1
Add MT8186 imp i2c wrapper clock controllers which provide clock gate control in i2c IP blocks. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Miles Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-04-25clk: mediatek: Add MT8186 apmixedsys clock supportChun-Jie Chen1-1/+2
Add MT8186 apmixedsys clock controller which provides Plls generated from SoC. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Miles Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-04-25clk: mediatek: Add MT8186 infrastructure clock supportChun-Jie Chen1-1/+1
Add MT8186 infrastructure clock controller which provides clock gate control for basic IP like pwm, uart, spi and so on. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Miles Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-04-25clk: mediatek: Add MT8186 topckgen clock supportChun-Jie Chen1-1/+1
Add MT8186 topckgen clock controller which provides muxes, dividers to handle variety clock selection in other IP blocks. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Miles Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-04-25clk: mediatek: Add MT8186 mcusys clock supportChun-Jie Chen1-0/+1
Add MT8186 mcusys clock controller which provides muxes to select the clock source of APMCU. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Miles Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-01-06clk: mediatek: add mt7986 clock supportSam Shih1-0/+4
Add MT7986 clock support, include topckgen, apmixedsys, infracfg, and ethernet subsystem clocks. Signed-off-by: Sam Shih <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Ryder Lee <[email protected]> [[email protected]: Fix typos in Kconfig, there are more existing typos from where they were copied from of but whatever] Signed-off-by: Stephen Boyd <[email protected]>
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