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path: root/drivers/clk/imx/clk-imx8mp.c
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2024-06-21clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rateMarek Vasut1-2/+2
The media_disp[12]_pix clock supply LCDIFv3 pixel clock output. These clocks are usually the only downstream clock from Video PLL on i.MX8MP. Allow these clocks to reconfigure the Video PLL, as that results in accurate pixel clock. If the Video PLL is not reconfigured, the pixel clock accuracy is low. Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-06-21clk: imx: imx8mp: fix clock tree update of TF-A managed clocksZhipeng Wang1-2/+2
On the i.MX8M*, the TF-A exposes a SiP (Silicon Provider) service for DDR frequency scaling. The imx8m-ddrc-devfreq driver calls the SiP and then does clk_set_parent on the DDR muxes to synchronize the clock tree. since commit 936c383673b9 ("clk: imx: fix composite peripheral flags"), these TF-A managed muxes have SET_PARENT_GATE set, which results in imx8m-ddrc-devfreq's clk_set_parent after SiP failing with -EBUSY: clk_set_parent(dram_apb_src, sys1_pll_40m);(busfreq-imx8mq.c) commit 926bf91248dd ("clk: imx8m: fix clock tree update of TF-A managed clocks") adds this method and enables 8mm, 8mn and 8mq. i.MX8MP also needs it. This is safe to do, because updating the Linux clock tree to reflect reality will always be glitch-free. Another reason to this patch is that powersave image BT music requires dram to be 400MTS, so clk_set_parent(dram_alt_src, sys1_pll_800m); is required. Without this patch, it will not succeed. Fixes: 936c383673b9 ("clk: imx: fix composite peripheral flags") Signed-off-by: Zhipeng Wang <[email protected]> Reviewed-by: Ahmad Fatoum <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-08-14clk: imx8mp: fix sai4 clockMarco Felsch1-5/+0
The reference manual don't mention a SAI4 hardware block. This would be clock slice 78 which is skipped (TRM, page 237). Remove any reference to this clock to align the driver with the reality. Fixes: 9c140d992676 ("clk: imx: Add support for i.MX8MP clock driver") Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Marco Felsch <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-06-12clk: imx: clk-imx8mp: improve error handling in imx8mp_clocks_probe()Yuxing Liu1-11/+13
Replace of_iomap() and kzalloc() with devm_of_iomap() and devm_kzalloc() which can automatically release the related memory when the device or driver is removed or unloaded to avoid potential memory leak. In this case, iounmap(anatop_base) in line 427,433 are removed as manual release is not required. Besides, referring to clk-imx8mq.c, check the return code of of_clk_add_hw_provider, if it returns negtive, print error info and unregister hws, which makes the program more robust. Fixes: 9c140d992676 ("clk: imx: Add support for i.MX8MP clock driver") Signed-off-by: Yuxing Liu <[email protected]> Reviewed-by: Dongliang Mu <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-04-09clk: imx: imx8mp: change the 'nand_usdhc_bus' clock to non-criticalHaibo Chen1-1/+1
The 'nand_usdhc_bus' clock is only need to be enabled when usdhc or nand module is active, so change it to non-critical clock type. Signed-off-by: Haibo Chen <[email protected]> Signed-off-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-04-09clk: imx: imx8mp: Add LDB root clockLiu Ying1-0/+1
This patch adds "media_ldb_root_clk" clock for the LDB in the MEDIAMIX subsystem. Reviewed-by: Sandor Yu <[email protected]> Signed-off-by: Liu Ying <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> Signed-off-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-04-09clk: imx: imx8mp: correct DISP2 pixel clock typePeng Fan1-1/+1
The MEDIA_DISP2_CLK_ROOT use ccm_ahb_channel, it is bus type. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-01-29clk: imx: remove clk_count of imx_register_uart_clocksPeng Fan1-1/+1
The clk count has been get with of_clk_get_parent_count, there is no need to pass clk_count from users. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-25clk: imx: rename imx_obtain_fixed_clk_hw() to imx_get_clk_hw_by_name()Dario Binacchi1-6/+6
The imx_obtain_fixed_clk_hw name was wrong and misleading. Renaming it to imx_get_clk_hw_by_name clarifies the purpose of the function, and will allow it to be used not only for fixed rate clocks but also in wider contexts. No functional changes intended. The replacements were made with the following command: grep -rl 'imx_obtain_fixed_clk_hw' ./ | \ xargs sed -i 's/imx_obtain_fixed_clk_hw/imx_get_clk_hw_by_name/g' Tested on a BSH SystemMaster (SMM) S2 board. Signed-off-by: Dario Binacchi <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-22clk: imx8mp: Add audio shared gateAbel Vesa1-1/+11
According to the RM, the CCGR101 is shared for the following root clocks: - AUDIO_AHB_CLK_ROOT - AUDIO_AXI_CLK_ROOT - SAI1_CLK_ROOT - SAI2_CLK_ROOT - SAI3_CLK_ROOT - SAI5_CLK_ROOT - SAI6_CLK_ROOT - SAI7_CLK_ROOT - PDM_CLK_ROOT IMX8MP_CLK_AUDIO_ROOT is same as AUDIO_AHB_CLK_ROOT which can avoid break any users. Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Shengjiu Wang <[email protected]> Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-21clk: imx: imx8mp: add shared clk gate for usb suspend clkLi Jun1-1/+3
32K usb suspend clock gate is shared with usb_root_clk, this shared clock gate was initially defined only for usb suspend clock, usb suspend clk is kept on while system is active or system sleep with usb wakeup enabled, so usb root clock is fine with this situation; with the commit cf7f3f4fa9e5 ("clk: imx8mp: fix usb_root_clk parent"), this clock gate is changed to be for usb root clock, but usb root clock will be off while usb is suspended, so usb suspend clock will be gated too, this cause some usb functionalities will not work, so define this clock to be a shared clock gate to conform with the real HW status. Fixes: 9c140d9926761 ("clk: imx: Add support for i.MX8MP clock driver") Cc: [email protected] # v5.19+ Tested-by: Alexander Stein <[email protected]> Signed-off-by: Li Jun <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-02clk: imx8mp: tune the order of enet_qos_root_clkPeng Fan1-1/+1
The enet_qos_root_clk takes sim_enet_root_clk as parent. When registering enet_qos_root_clk, it will be put into clk orphan list, because sim_enet_root_clk is not ready. When sim_enet_root_clk is ready, clk_core_reparent_orphans_nolock will set enet_qos_root_clk parent to sim_enet_root_clk. Because CLK_OPS_PARENT_ENABLE is set, sim_enet_root_clk will be enabled and disabled during the enet_qos_root_clk reparent phase. All the above are correct. But with M7 booted early and using enet, M7 enet feature will be broken, because clk driver probe phase disable the needed clks, in case M7 firmware not configure sim_enet_root_clk. And tune the order would also save cpu cycles. Reviewed-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-05-17clk: imx8mp: fix usb_root_clk parentPeng Fan1-1/+1
According to reference mannual CCGR77(usb) sources from hsio_axi, fix it. Fixes: 9c140d9926761 ("clk: imx: Add support for i.MX8MP clock driver") Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2022-05-02clk: imx8mp: add clkout1/2 supportLucas Stach1-0/+14
clkout1 and clkout2 allow to supply clocks from the SoC to the board, which is used by some board designs to provide reference clocks. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2022-04-18clk: imx8mp: Add DISP2 pixel clockMarek Vasut1-2/+3
Add pixel clock for second LCDIFv3 interface. Both LCDIFv3 interfaces use the same set of parent clock, so deduplicate imx8mp_media_disp1_pix_sels into common imx8mp_media_disp_pix_sels and use it for both. Signed-off-by: Marek Vasut <[email protected]> Cc: Abel Vesa <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: NXP Linux Team <[email protected]> Cc: Peng Fan <[email protected]> Cc: Shawn Guo <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2022-04-12clk: imx: Remove the snvs clockJacky Bai1-1/+0
The SNVS moudule is not used only by the linux, it may also used by other SW component is secure world. No sense to populate it in linux, so remove it. Signed-off-by: Jacky Bai <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2022-04-12clk: imx: add mcore_booted module paratemterPeng Fan1-0/+2
Add mcore_booted boot parameter which could simplify AMP clock management. To i.MX8M, there is CCM(clock control Module) to generate clock root clock, anatop(analog PLL module) to generate PLL, and CCGR (clock gating) to gate clocks to peripherals. As below: anatop->ccm->ccgr->peripheral Linux handles the clock management and the auxiliary core is under control of Linux. Although there is per hardware domain control for CCGR and CCM, auxiliary core normally only use CCGR hardware domain control to avoid linux gate off the clk to peripherals and leave CCM ana anatop to Linux. Per NXP hardware design, because CCGR already support gate to peripherals, and clk root gate power leakage is negligible. So when in AMP case, we could not register the clk root gate. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2022-03-04clk: imx8mp: remove SYS PLL 1/2 clock gatesPeng Fan1-32/+16
Remove the PLL 1/2 gates as it make AMP clock management harder without obvious benifit. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2022-02-21clk: imx8mp: Add missing IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT clockLaurent Pinchart1-0/+1
The IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT clock derives from the media_mipi_phy1_ref clock and is gated by the shared media clock gate. Its identifier is defined in dt-bindings/clock/imx8mp-clock.h but its definition is missing from the driver. Add it. Signed-off-by: Laurent Pinchart <[email protected]> Reviewed-by: Paul Elder <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2021-11-22clk: imx8mp: Fix the parent clk of the audio_root_clkHui Wang1-1/+1
Having the parent of the audio_root_clk set to ipg_root in the clk-imx8mp.c, there is a hang happening when the audiomix IP regs are accessed. Switch parent to audio_ahb. And we could also refer to the section "5.1.4 System Clocks" of the IMX8MPRM.pdf, the parent clk of CCGR101 (Audiomix) is the AUDIO_AHB_CLK_ROOT. Signed-off-by: Hui Wang <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2021-06-14clk: imx: Remove the audio ipg clock from imx8mpJacky Bai1-1/+0
There is no audio ipg clock on i.MX8MP, so remove this from the clock driver. Signed-off-by: Jacky Bai <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Abel Vesa <[email protected]>
2021-04-04clk: imx8mp: Remove the none exist pcie clocksRichard Zhu1-15/+0
In the i.MX8MP PCIe design, the PCIe PHY REF clock comes from external OSC or internal system PLL. It is configured in the IOMUX_GPR14 register directly, and can't be contolled by CCM at all. Remove the PCIE PHY clock from clock driver to clean up codes. There is only one PCIe in i.MX8MP, remove the none exist second PCIe related clocks. Remove the none exsits clocks IDs together. Signed-off-by: Richard Zhu <[email protected]> Reviewed-by: Jason Liu <[email protected]> Signed-off-by: Abel Vesa <[email protected]>
2021-04-04clk: imx: Fix reparenting of UARTs not associated with stdoutAdam Ford1-16/+1
Most if not all i.MX SoC's call a function which enables all UARTS. This is a problem for users who need to re-parent the clock source, because any attempt to change the parent results in an busy error due to the fact that the clocks have been enabled already. clk: failed to reparent uart1 to sys_pll1_80m: -16 Instead of pre-initializing all UARTS, scan the device tree to see which UART clocks are associated to stdout, and only enable those UART clocks if it's needed early. This will move initialization of the remaining clocks until after the parenting of the clocks. When the clocks are shutdown, this mechanism will also disable any clocks that were pre-initialized. Fixes: 9461f7b33d11c ("clk: fix CLK_SET_RATE_GATE with clock rate protection") Suggested-by: Aisheng Dong <[email protected]> Signed-off-by: Adam Ford <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Tested-by: Ahmad Fatoum <[email protected]> Signed-off-by: Abel Vesa <[email protected]>
2020-12-21Merge tag 'clk-for-linus' of ↵Linus Torvalds1-2/+2
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The core framework got some nice improvements this time around. We gained the ability to get struct clk pointers from a struct clk_hw so that clk providers can consume the clks they provide, if they need to do something like that. This has been a long missing part of the clk provider API that will help us move away from exposing a struct clk pointer in the struct clk_hw. Tracepoints are added for the clk_set_rate() "range" functions, similar to the tracepoints we already have for clk_set_rate() and we added a column to debugfs to help developers understand the hardware enable state of clks in case firmware or bootloader state is different than what is expected. Overall the core changes are mostly improving the clk driver writing experience. At the driver level, we have the usual collection of driver updates and new drivers for new SoCs. This time around the Qualcomm folks introduced a good handful of clk drivers for various parts of three or four SoCs. The SiFive folks added a new clk driver for their FU740 SoCs, coming in second on the diffstat and then Atmel AT91 and Amlogic SoCs had lots of work done after that for various new features. One last thing to note in the driver area is that the i.MX driver has gained a new binding to support SCU clks after being on the list for many months. It uses a two cell binding which is sort of rare in clk DT bindings. Beyond that we have the usual set of driver fixes and tweaks that come from more testing and finding out that some configuration was wrong or that a driver could support being built as a module. Summary: Core: - Add some trace points for clk_set_rate() "range" functions - Add hardware enable information to clk_summary debugfs - Replace clk-provider.h with of_clk.h when possible - Add devm variant of clk_notifier_register() - Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw New Drivers: - Bindings for Canaan K210 SoC clks - Support for SiFive FU740 PRCI - Camera clks on Qualcomm SC7180 SoCs - GCC and RPMh clks on Qualcomm SDX55 SoCs - RPMh clks on Qualcomm SM8350 SoCs - LPASS clks on Qualcomm SM8250 SoCs Updates: - DVFS support for AT91 clk driver - Update git repo branch for Renesas clock drivers - Add camera (CSI) and video-in (VIN) clocks on Renesas R-Car V3U - Add RPC (QSPI/HyperFLASH) clocks on Renesas RZ/G2M, RZ/G2N, and RZ/G2E - Stop using __raw_*() I/O accessors in Renesas clk drivers - One more conversion of DT bindings to json-schema - Make i.MX clk-gate2 driver more flexible - New two cell binding for i.MX SCU clks - Drop of_match_ptr() in i.MX8 clk drivers - Add arch dependencies for Rockchip clk drivers - Fix i2s on Rockchip rk3066 - Add MIPI DSI clks on Amlogic axg and g12 SoCs - Support modular builds of Amlogic clk drivers - Fix an Amlogic Video PLL clock dependency - Samsung Kconfig dependencies updates for better compile test coverage - Refactoring of the Samsung PLL clocks driver - Small Tegra driver cleanups - Minor fixes to Ingenic and VC5 clk drivers - Cleanup patches to remove unused variables and plug memory leaks" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (134 commits) dt-binding: clock: Document canaan,k210-clk bindings dt-bindings: Add Canaan vendor prefix clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts" clk: ingenic: Fix divider calculation with div tables clk: sunxi-ng: Make sure divider tables have sentinel clk: s2mps11: Fix a resource leak in error handling paths in the probe function clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9 clk: si5351: Wait for bit clear after PLL reset clk: at91: sam9x60: remove atmel,osc-bypass support clk: at91: sama7g5: register cpu clock clk: at91: clk-master: re-factor master clock clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz clk: at91: sama7g5: decrease lower limit for MCK0 rate clk: at91: sama7g5: remove mck0 from parent list of other clocks clk: at91: clk-sam9x60-pll: allow runtime changes for pll clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics clk: at91: clk-master: add 5th divisor for mck master clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT dt-bindings: clock: at91: add sama7g5 pll defines clk: at91: sama7g5: fix compilation error ...
2020-11-10clk: imx8mp: drop of_match_ptr from of_device_id tableKrzysztof Kozlowski1-1/+1
The driver can match only via the DT table so the table should be always used and the of_match_ptr does not have any sense (this also allows ACPI matching via PRP0001, even though it might be not relevant here). This fixes compile warning (!CONFIG_OF && !CONFIG_MODULES): drivers/clk/imx/clk-imx8mp.c:751:34: warning: ‘imx8mp_clk_of_match’ defined but not used [-Wunused-const-variable=] Reported-by: kernel test robot <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-11-04clk: imx8m: fix bus critical clk registrationPeng Fan1-5/+5
noc/axi/ahb are bus clk, not peripheral clk. Since peripheral clk has a limitation that for peripheral clock slice, IP clock slices must be stopped to change the clock source. However if the bus clk is marked as critical clk peripheral, the assigned clock parent operation will fail. So we added CLK_SET_PARENT_GATE flag to avoid glitch. And add imx8m_clk_hw_composite_bus_critical for bus critical clock usage Fixes: 936c383673b9e ("clk: imx: fix composite peripheral flags") Reviewed-by: Abel Vesa <[email protected]> Reported-by: Abel Vesa <[email protected]> Signed-off-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-11-01clk: imx: remove redundant assignment to pointer npColin Ian King1-1/+1
Pointer np is being initialized with a value that is never read and it is being updated with a value later on. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <[email protected]> Reviewed-by: Dong Aisheng <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-08-31clk: imx: Correct the memrepair clock on imx8mpJacky Bai1-10/+4
The root clock slice at offset 0xbf80 should be memrepair clock, so correct it. And this clock should be always on to make sure the memory repair function can works well. Signed-off-by: Jacky Bai <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-08-31clk: imx: Correct the root clk of media ldb on imx8mpJacky Bai1-5/+5
The root clock slice at 0xbf00 is media_ldb clock, not csi_phy2_ref, so correct it. Signed-off-by: Jacky Bai <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-08-22clk: imx8m: Support module buildAnson Huang1-0/+4
Change configuration to "tristate", add module author, description and license to support building i.MX8M SoCs clock driver as module. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Dong Aisheng <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-06-23clk: imx8mp: add mu root clkPeng Fan1-0/+1
Add mu root clk for mu mailbox usage. Reviewed-by: Dong Aisheng <[email protected]> Signed-off-by: Peng Fan <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-05-21clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slicePeng Fan1-12/+12
Switch the bus clk use imx8m_clk_hw_composite_bus, then we could avoid possible issue when setting mux of the clk. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Dong Aisheng <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-05-20clk: imx8mp: use imx8m_clk_hw_composite_core to simplify codePeng Fan1-31/+16
Use imx8m_clk_hw_composite_core to simpliy clks that belong to core clk slice. Reviewed-by: Leonard Crestez <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Dong Aisheng <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-05-20clk: imx8mp: Define gates for pll1/2 fixed dividersPeng Fan1-18/+36
Inspried from commit e8688fe8df7d ("clk: imx8mn: Define gates for pll1/2 fixed dividers") On imx8mp there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2 each with their own gate. Only one of these gates (the one "dividing" by one) is currently defined and it's incorrectly set as the parent of all the fixed-factor dividers. Add the other 8 gates to the clock tree between sys_pll1/2_bypass and the fixed dividers. Reviewed-by: Dong Aisheng <[email protected]> Reviewed-by: Leonard Crestez <[email protected]> Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-05-20clk: imx: imx8mp: fix pll mux bitPeng Fan1-10/+10
Same to i.MX8MN/i.MX8MM, pll BYPASS bit should be kept inside pll driver for glitchless freq setting following spec. If exposing the bit, that means pll driver and clk driver has two paths to touch this bit, which is wrong. So use EXT_BYPASS bit here. Reviewed-by: Dong Aisheng <[email protected]> Reviewed-by: Leonard Crestez <[email protected]> Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-05-20clk: imx8m: drop clk_hw_set_parent for A53Peng Fan1-3/+0
The parent settings have been moved to dtsi, we no need to set parent here. And clk_hw_set_parent will trigger lockdep warning, because this api not have prepare_lock. Reported-by: Leonard Crestez <[email protected]> Reviewed-by: Dong Aisheng <[email protected]> Reviewed-by: Leonard Crestez <[email protected]> Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-04-05Merge tag 'clk-for-linus' of ↵Linus Torvalds1-7/+17
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "There's not much to see in the core framework this time around. Instead the majority of the diff is the normal collection of driver additions for new SoCs and non-critical clk data fixes and updates. The framework must be middle aged. The two biggest directories in the diffstat show that the Qualcomm and Unisoc support added a handful of big drivers for new SoCs but that's not really the whole story because those new drivers tend to add large numbers of lines of clk data. There's a handful of AT91 clk drivers added this time around too and a bunch of improvements to drivers like the i.MX driver. All around lots of updates and fixes in various clk drivers which is good to see. The core framework has only one real major change which has been baking in next for the past couple months. It fixes the framework so that it stops caching a clk's phase when the phase clk_op returns an error. Before this change we would consider some negative errno as a phase and that just doesn't make sense. Core: - Don't show clk phase when it is invalid New Drivers: - Add support for Unisoc SC9863A clks - Qualcomm SM8250 RPMh and MSM8976 RPM clks - Qualcomm SM8250 Global Clock Controller (GCC) support - Qualcomm SC7180 Modem Clock Controller (MSS CC) support - EHRPWM's TimeBase clock(TBCLK) for TI AM654 SoCs - Support PMC clks on at91sam9n12, at91rm9200, sama5d3, and at91sam9g45 SoCs Updates: - GPU GX GDSC support on Qualcomm sc7180 - Fixes and improvements for the Marvell MMP2/MMP3 SoC clk drivers - A series from Anson to convert i.MX8 clock bindings to json-schema - Update i.MX pll14xx driver to include new frequency entries for pll1443x table, and return error for invalid PLL type - Add missing of_node_put() call for a number of i.MX clock drivers - Drop flag CLK_IS_CRITICAL from 'A53_CORE' mux clock, as we already have the flag on its child cpu clock - Fix a53 cpu clock for i.MX8 drivers to get it source from ARM PLL via CORE_SEL slice, and source from A53 CCM clk root when we need to change ARM PLL frequency. Thus, we can support core running above 1GHz safely - Update i.MX pfdv2 driver to check zero rate and use determine_rate for getting the best rate - Add CLKO2 for imx8mm, SNVS clock for imx8mn, and PXP clock for imx7d - Remove PMC clks from Tegra clk driver - Improved clock/reset handling for the Renesas R-Car USB2 Clock Selector - Conversion to json-schema of the Renesas CPG/MSSR DT bindings - Add Crypto clocks on Renesas R-Car M3-W/W+, M3-N, E3, and D3 - Add RPC (QSPI/HyperFLASH) clocks on Renesas R-Car H3, M3-W/W+, and M3-N - Update Amlogic audio clock gate hierarchy for meson8 and gxbb - Update Amlogic g12a spicc clock sources - Support for Ingenic X1000 TCU clks" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (146 commits) clk: sprd: fix to get a correct ibias of pll dt-bindings: imx8mm-clock: Fix the file path dt-bindings: imx8mq-clock: Fix the file path clk: qcom: rpmh: Drop unnecessary semicolons clk: qcom: rpmh: Simplify clk_rpmh_bcm_send_cmd() clk: tegra: Use NULL for pointer initialization clk: sprd: add clocks support for SC9863A clk: sprd: support to get regmap from parent node clk: sprd: Add macros for referencing parents without strings clk: sprd: Add dt-bindings include file for SC9863A dt-bindings: clk: sprd: add bindings for sc9863a clock controller dt-bindings: clk: sprd: rename the common file name sprd.txt to SoC specific clk: sprd: add gate for pll clocks MAINTAINERS: dt: update reference for arm-integrator.txt clk: mmp2: Fix bit masks for LCDC I/O and pixel clocks clk: mmp2: Add clock for fifth SD HCI on MMP3 dt-bindings: marvell,mmp2: Add clock id for the fifth SD HCI on MMP3 clk: mmp2: Add clocks for the thermal sensors dt-bindings: marvell,mmp2: Add clock ids for the thermal sensors clk: mmp2: add the GPU clocks ...
2020-03-16clk: imx8mp: Correct the enet_qos parent clockFugang Duan1-1/+1
enet_qos is for eqos tsn AXI bus clock whose clock source is from ccm_enet_axi_clk_root, and controlled by CCM_CCGR59(offset 0x43b0) and CCM_CCGR64(offset 0x4400), so correct enet_qos root clock's parent clock to sim_enet. Fixes: 9c140d992676 ("clk: imx: Add support for i.MX8MP clock driver") Signed-off-by: Fugang Duan <[email protected]> Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-03-16clk: imx8mp: Correct IMX8MP_CLK_HDMI_AXI clock parentAnson Huang1-1/+1
IMX8MP_CLK_HDMI_AXI should be from imx8mp_media_axi_sels instead of imx8mp_media_apb_sels, fix it. Fixes: 9c140d992676 ("clk: imx: Add support for i.MX8MP clock driver") Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-03-11clk: imx8mp: A53 core clock no need to be criticalAnson Huang1-4/+4
'A53_CORE' is just a mux and no need to be critical, being critical will cause its parent clock always ON which does NOT make sense, to make sure CPU's hardware clock source NOT being disabled during clock tree setup, need to move the 'A53_SRC'/'A53_CORE' reparent operations to after critical clock 'ARM_CLK' setup finished. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-02-24clk: imx: imx8mp: fix a53 cpu clockPeng Fan1-4/+12
The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root signoff timing is 1Ghz, however the A53 core which sources from CCM root could run above 1GHz which voilates the CCM. There is a CORE_SEL slice before A53 core, we need configure the CORE_SEL slice source from ARM PLL, not A53 CCM clk root. The A53 CCM clk root should only be used when need to change ARM PLL frequency. Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out. Configure a53 ccm root sources from 800MHz sys pll Configure a53 core sources from arm_pll_out Mark arm_a53_core as critical clk Reviewed-by: Jacky Bai <[email protected]> Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-02-24clk: imx8mp: Rename the IMX8MP_CLK_HDMI_27M clockAnson Huang1-2/+2
On i.MX8MP, internal HDMI 27M clock is actually 24MHz, so rename the IMX8MP_CLK_HDMI_27M to IMX8MP_CLK_HDMI_24M. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-02-19clk: imx8mp: Include slab.h instead of clkdev.hAnson Huang1-1/+1
slab.h is necessary and included indirectly by clkdev.h, actually, there is nothing in use from clkdev.h, so just include slab.h instead of clkdev.h. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-02-17clk: imx8mp: Add missing of_node_put()Anson Huang1-0/+1
After finishing using device node got from of_find_compatible_node(), of_node_put() needs to be called. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-02-14clk: imx: imx8mp: add ocotp root clkPeng Fan1-0/+1
Add ocotp root clk, then when using nvmem to read fuse, clk could be managed. Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-01-12clk: imx: Add support for i.MX8MP clock driverAnson Huang1-0/+764
Add clock driver support for i.MX8MP which is a new SoC of i.MX8M family. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
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